NCP5111DR2G Просмотр технического описания (PDF) - ON Semiconductor
Номер в каталоге
Компоненты Описание
производитель
NCP5111DR2G Datasheet PDF : 14 Pages
| |||
NCP5111
IN
DRV_HI
DRV_LO
Note: DRV_HI output is in phase with the input.
Figure 4. Input/Output Timing Diagram
IN
DRV_HI
DRV_LO
50%
ton
Dead Time
toff
tf
90%
10%
50%
tr
90%
10%
toff
90%
tf
10%
Dead Time
ton
ton = toff + DT
Figure 5. Timing Definitions
tr
90%
10%
IN
50%
50%
toff_HI
DRV_HI
DRV_LO
Dead Time 1
toff_LO
10%
90%
Dead Time 2
90%
Matching Delay 1 = toff_HI − toff_LO
Matching Delay 2 = (toff_LO + DT1) − (toff_HI + DT2)
10%
Figure 6. Matching Propagation Delay
www.onsemi.com
5
Share Link: 