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HI5728IN-T

10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter

Intersil 

HI5728

Electrical Specifications AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values. Data given is

per channel except for “POWER SUPPLY CHARACTERISTICS” on page 8 (Continued)

PARAMETER

TEST CONDITIONS

HI5728IN

TA = -40°C TO +85°C

MIN

MAX

(Note 11) TYP (Note 11)

UNITS

AC CHARACTERISTICS (Per Channel) - HI5728IN - 125MHz

Spurious Free Dynamic Range,

fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7)

-

75

-

dBc

SFDR Within a Window

fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7)

-

76

-

dBc

fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7)

-

75

-

dBc

fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7)

-

76

-

dBc

fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7)

-

78

-

dBc

Total Harmonic Distortion (THD) to

Nyquist

fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7)

fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7)

-

71

-

dBc

-

71

-

dBc

fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7)

-

76

-

dBc

Spurious Free Dynamic Range,

fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7)

-

54

-

dBc

SFDR to Nyquist

fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7)

-

64

-

dBc

fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7)

-

52

-

dBc

fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7)

-

60

-

dBc

fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7)

-

68

-

dBc

fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7)

-

74

-

dBc

fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7)

-

63

-

dBc

fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7)

-

55

-

dBc

fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)

-

68

-

dBc

fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7)

-

73

-

dBc

fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7)

-

73

-

dBc

AC CHARACTERISTICS (Per Channel) - HI5728/6IN - 60MHz

Spurious Free Dynamic Range,

fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7)

-

75

-

dBc

SFDR Within a Window

fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7)

-

76

-

dBc

fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7)

-

78

-

dBc

Total Harmonic Distortion (THD) to

Nyquist

fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7)

fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7)

-

71

-

dBc

-

76

-

dBc

Spurious Free Dynamic Range,

fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7)

-

56

-

dBc

SFDR to Nyquist

fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7)

-

63

-

dBc

fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7)

-

55

-

dBc

fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)

-

68

-

dBc

fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7)

-

73

-

dBc

fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7)

-

73

-

dBc

fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7)

-

71

-

dBc

VOLTAGE REFERENCE

Internal Reference Voltage, VFSADJ Voltage at Pin 22 with Internal Reference

Internal Reference Voltage Drift

1.04 1.16 1.28

-

±60

-

V

ppm/°C

Internal Reference Output Current

Sink/Source Capability

-

0.1

-

µA

Reference Input Impedance

-

1

-

MΩ

Reference Input Multiplying

Bandwidth

(Note 7)

-

1.4

-

MHz

DIGITAL INPUTS D9-D0, CLK (Per Channel)

Input Logic High Voltage with

5V Supply, VIH

(Note 3)

3.5

5

-

V

7

FN4321.5

January 22, 2010

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