HI5721-EVS Просмотр технического описания (PDF) - Intersil

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HI5721-EVS

10-Bit, 125MSPS, High Speed D/A Converter

Intersil 

HI5721

-0.6 TO -1.2V

1MHz (MAX)

RSET

RT

18Ω

HI5721

20

RSET

19

CTRL AMP IN

18

CTRL AMP

OUT

17

REF IN

FIGURE 19. LOW FREQUENCY MULTIPLYING CIRCUIT

If higher multiplying frequencies are desired, the reference

input can be directly driven. The analog signal range is -3.3V

to -4.25V. The multiplying signal must be capacitively

coupled into REF IN onto a DC bias between -3.3V to -4.25V

(-3.8V typically).

HI5721

2nF 383Ω

50Ω 120Ω

17

REF IN

≅ -3.8V

AVEE

FIGURE 20. WIDEBAND MULTIPLYING CIRCUIT

Outputs

The outputs IOUT and IOUT are complementary current

outputs. Current is steered to either IOUT or IOUT in

proportion to the digital input code. The sum of the two

currents is always equal to the full scale current minus one

LSB. The current output can be converted to a voltage by

using a load resistor. Both current outputs should have the

same load resistor (64Ω typically). By using a 64Ω load on

the output, a 50Ω effective output resistance (ROUT) is

achieved due to the 227Ω (±15%) parallel resistance seen

looking back into the output. This is the nominal value of the

R2R ladder of the DAC. The 50Ω output is needed for

matching the output with a 50Ω line. The load resistor should

be chosen so that the effective output resistance (ROUT)

matches the line resistance. The output voltage is:

VOUT = IOUT x ROUT .

IOUT is defined in the reference section. The compliance

range of the output is from -1.5V to 3V, with a 1VP-P voltage

swing allowed within this range. However, if it is desired that

the output be offset above zero volts, it is necessary that pin

19 (ARTN) be connected to the same voltage as the load

resistor, not to exceed 3V.

Glitch

TABLE 1. INPUT CODING vs CURRENT OUTPUT

INPUT CODE (D9-D0)

11 1111 1111

IOUT (mA)

-20.48

IOUT (mA)

0

10 0000 0000

-10.24

-10.24

00 0000 0000

0

-20.48

The output glitch of the HI5721 is measured by summing the

area under the switching transients after an update of the

DAC. Glitch is caused by the time skew between bits of the

incoming digital data. Typically the switching time of digital

inputs are asymmetrical meaning that the turn off time is

faster than the turn on time (TTL designs). Unequal delay

paths through the device can also cause one current source

to change before another. To minimize this the Intersil

HI5721 employes an internal register, just prior to the current

sources, that is updated on the clock edge. Lastly the worst

case glitch usually happens at the major transition i.e.,

01 1111 1111 to 10 0000 0000. But in the HI5721 the glitch

is moved to the 00 0001 1111 to 11 1110 0000 transition.

This is achieved by the split R/2R segmented current source

architecture. This decreases the amount of current switching

at any one time and makes the glitch practically constant

over the entire output range. By making the glitch a constant

size over the entire output range this effectively integrates

this error out of the end application.

In measuring the output glitch of the HI5721 the output is

terminated into a 64Ω load. The glitch is measured at the

major carrys throughout the DAC’s output range.

The glitch energy is calculated by measuring the area under

the voltage-time curve. Figure 21 shows the area considered

as glitch when changing the DAC output. Units are typically

specified in picoVolt • seconds (pV • s).

HI5721

(20) IOUT

125MHz SCOPE

LOW PASS

FILTER

64Ω

50Ω

FIGURE 21. GLITCH TEST CIRCUIT

11

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