NB3N502DG Просмотр технического описания (PDF) - ON Semiconductor
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NB3N502DG Datasheet PDF : 5 Pages
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NB3N502
X1/CLK 1
VDD 2
GND 3
REF 4
8 X2
7 S1
6 S0
5 CLKOUT
Figure 2. Pin Configuration (Top View)
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1*
S0**
Multiplier
L
L
2X
L
H
5X
M
L
3X
M
H
3.33X
H
L
4X
H
H
2.5X
L = GND
H = VDD
M = OPEN (unconnected)
* Pin S1 defaults to M when left open
** Pin S0 defaults to H when left open
Table 2. OUTPUT FREQUENCY EXAMPLES
Output Frequency (MHz)
20 25 33.3 48 50 54 64 66.66 75 100 108 120 135
Input Frequency (MHz)
10 10
10
16 20 13.5 16
20
15 20 27 24 27
S1, S0
0 ,0 1, 1 M, 1 M, 0 1, 1 1, 0 1, 0 M, 1 0, 1 0, 1 1, 0 0, 1 0, 1
Table 3. PIN DESCRIPTION
Pin #
Name
I/O
1
X1/CLK
Input
2
VDD
3
GND
Power Supply
Power Supply
4
REF
CMOS/TTL Output
5
CLKOUT
CMOS/TTL Output
6
S0
CMOS/TTL Input
7
S1
Three−level Input
8
X2
Crystal Input
Description
Crystal or External Reference Clock Input
Positive Supply Voltage (3 V to 5.5 V)
0 V Ground.
Buffered Crystal Oscillator Clock Output
Clock Output
Multiplier Select Pin − Connect to VDD or GND. Internal Pull−up Resistor.
Multiplier Select Pin − Connect to VDD, GND or Float to M.
Crystal Input − Do Not Connect when Providing an External Clock Reference
Table 4. ATTRIBUTES
Characteristic
Value
ESD Protection
Human Body Model
Machine Model
> 8 kV
> 600 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
6700 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
http://onsemi.com
2
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