HI3197JCQ Просмотр технического описания (PDF) - Intersil
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HI3197JCQ Datasheet PDF : 25 Pages
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HI3197
Pin Descriptions and I/O Pin Equivalent Circuits (Continued)
PIN NO
22
SYMBOL
RESET/T
TYPICAL
VOLTAGE
I/O
LEVEL
I TTL
DVCC1
EQUIVALENT CIRCUIT
23
RESETP/E I PECL
24
RESETN/E I PECL
22
DGND1
DVCC1
23
24
VREF
DESCRIPTION
Reset signal input. When the multi-
ple HI3197 are operated at a time
for MUX.1A or MUX.1B mode, the
start timing of the internal 1/2 fre-
quency divider circuits should be
matched.
At this time, the reset signal is
used; when the reset signal is the
TTL level, Pin 22 is used and Pins
23 and 24 are left open. When the
reset signal is the PECL level, Pins
23 and 24 are used and Pin 22 is
left open. For the PECL level, oper-
ation is possible only with RE-
SETP/E as with the case for the
clock. The reset signal polarity can
be set by Pin 39 (RPOLARITY).
Leave the reset pin open when the
other modes are used.
DGND1
25
DGND2
Single Power
Supply: GND Dual
Power Supplies:
-5V
26
C1
I TTL
27
C2
I TTL
DVCC1
28
C3
I TTL
26
27
28
DGND1
29
DVCC2
Single Power
Supply: +5V Dual
Power Supplies:
GND
30
AVCC0
31
OUTN
O AVCC0 - VFS
RO
32
AOUTP
O AVCC0 - VFS
Digital Power Supply.
Function setting.
VREF
AVCC0
RO
31
32
Digital Power Supply.
Analog Output Power Supply.
D/A Negative Output. The inversion
of the D/A positive output pin is out-
put. Terminate the inversion without
pin with 50Ω when the inversion out-
put is not used and the positive out-
put is terminated with 50Ω.
D/A positive output.
33
AGND2
Single Power
Supply: GND
Dual Power
Supplies: -5V
AGND2
Analog Ground.
4
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