HI3197JCQ Просмотр технического описания (PDF) - Intersil

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HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

HI3197

CLOCK

RESET SIGNAL

(WHEN ACTIVE LOW)

INTERNALLY 1/2

FREQUENCY-DIVIDED SIGNAL

(THIS SIGNAL CANNOT BE OBSERVED)

tH-RST

tS

tS-RST

tH

DATA INPUT SIGNAL

HI3197 (MUX. 1B MODE)

CLOCK INPUT PIN

1/2

RESET INPUT PIN

DA0 TO DA9

DB0 TO DB9

AFTER THE RESET IS RELEASED, THE INTERNAL 1/2 FREQUENCY-DIVIDED SIGNAL COMMENCES AT THE FIRST CLOCK EDGE, SO BE SURE TO INPUT

THE DATA IN A MANNER THAT SATISFIES THE SETUP TIME (TS) AND HOLD TIME (TH) WITH RESPECT TO THIS CLOCK EDGE.

FIGURE 8A.

CLK

HI3197

CLK

HI3197

CLK

CLK

INTERNALLY 1/2

FREQUENCY-DIVIDED

SIGNAL

INTERNALLY 1/2

FREQUENCY-DIVIDED

SIGNAL

FIGURE 8B. EXAMPLE WHEN NOT USING THE RESET SIGNAL

CLK

RESET

SIGNAL

HI3197

CLK

RESET

HI3197

CLK

RESET

CLK

RESET SIGNAL

(WHEN ACTIVE LOW)

INTERNALLY 1/2

FREQUENCY-DIVIDED

SIGNAL

INTERNALLY 1/2

FREQUENCY-DIVIDED

SIGNAL

FIGURE 8C. EXAMPLE WHEN USING THE RESET SIGNAL

FIGURE 8. MUX.1B MODE

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