HI3197JCQ Просмотр технического описания (PDF) - Intersil

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HI3197JCQ

10-Bit, 125 MSPS D/A Converter

Intersil 

HI3197

Block Diagram and Timing Charts (Continued)

CLK

C2

INPUT DATA A

INPUT DATA B

LATCH

INPUT LATCH A

INPUT LATCH B

SELECT

LATCH

DAC

FIGURE 14A. BLOCK DIAGRAM (SELE.A, SELE.B MODE)

ANALOG OUT

tPW1 tPW0

tPD (A)

tPD (B)

CLK

C2

INPUT DATA A N - 2

INPUT DATA B N - 1

C2 M/S OUT

0

tS tH

N

N+1

N-4

1

0

tH-C2

tS-C2

1

N+2

N+3

tDO

N-2

N+4

N+5

SELE. A

N

N+6

N+7

SELE. B

tDO

N+2

N+8

N+9

N+5

N+7

FIGURE 14B. TIMING CHART (SELE.A, SELE.B MODE)

NOTE: In SELE.A and SELE.B modes, input Data A or Data B is selected and the selected data can be analog output. When C1 = 1 and C3 = 0,

Data A is selected for C2 = 0, and Data B is selected for C2 = 1.

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