NB100LVEP221(2003) Просмотр технического описания (PDF) - ON Semiconductor

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NB100LVEP221
(Rev.:2003)

2.5V/3.3V
1:20 Differential HSTL/ECL/PECL Clock Driver

ON Semiconductor 

NB100LVEP221

HSTL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V

0°C

25°C

85°C

Symbol

Characteristic

Min Typ Max

Min Typ Max

Min Typ Max Unit

VIH

Input HIGH Voltage

CLK1/CLK1 Vx+100

VIL

Input LOW Voltage

CLK1/CLK1 -300

VX

Differential Configuration Cross

680

Point Voltage

1600 Vx+100

Vx-100

900

-300

680

1600 Vx+100

Vx-100

900

-300

680

1600 mV

Vx-100 mV

900 mV

IIH

Input HIGH Current

IIL

Input LOW Current

CLK1

CLK1

-150

-150

-250

150 -150

-150

-250

150 -150

-150

-250

150 mA

mA

NOTE: 100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.

The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 to -3.8 V or VCC = 2.375 to 3.8 V; VEE = 0 V (Note 15)

-40 °C

25°C

85°C

Symbol

Characteristic

Min Typ Max Min Typ Max Min Typ Max Unit

VOpp

Differential Output Voltage

(Figure 3)

fout < 50 MHz 550 700

600 700

600 700

mV

fout < 0.8 GHz 550 700

550 700

500 700

mV

fout < 1.0 GHz 500 700

500 700

400 600

mV

tPLH/tPHL Propagation Delay (Differential Configuration)

CLK0-Qx

CLK1-Qx

540 600

590 640

540 660

590 710

540 750 ps

590 800 ps

tskew

Within-Device Skew (Note 16)

Device-to-Device Skew (Note 17)

15 50

40 200

15 50

40 200

15 50 ps

40 200 ps

tJITTER

VPP

Random Clock Jitter (RMS) (Figure 3)

Input Swing (Differential Configuration)

(Note 18) (Figure 4)

CLK0 400

CLK1 HSTL 300

1

2

800 1200 400

800 1000 300

1

2

800 1200 400

800 1000 300

1

2 ps

800 1200 mV

800 1000 mV

DCO

Output Duty Cycle

49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 %

tr/tf

Output Rise/Fall Time (20%-80%)

100 200 300 100 200 300 150 250 350 ps

15. Measured with 750 mV source (LVPECL) or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC-2 V.

16. Skew is measured between outputs under identical transitions and conditions on any one device.

17. Device-to-Device skew for identical transitions, outputs and VCC levels.

18. VPP is the differential configuration input voltage swing required to maintain AC characteristics.

900

10

9

800

8

700

7

600

6

5

500

4

400

3

2

300

1

200

0.1

0.2

0.4

0.6

0.8

0

1.0

fIN, INPUT FREQUENCY (GHz)

Figure 3. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC - VEE = 3.3 V @ 255C)

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