PCK2000 Просмотр технического описания (PDF) - Philips Electronics
Номер в каталоге
Компоненты Описание
производитель
PCK2000 Datasheet PDF : 14 Pages
| |||
Philips Semiconductors
CK97 (66/100MHz) System Clock Generator
Product specification
PCK2000
AC CHARACTERISTICS
VDDREF = VDDPCI (0–1) = VDD48MHz = 3.3V ± 5%; VDDAPIC = VDDCPU (0–1) = 2.5V ± 5%; fcrystal = 14.31818 MHz
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
THKP (tP)
THKH (tH)
THKL (tL)
THKP (tP)
THKH (tH)
THKL (tL)
THRISE (tR)
THFALL (tF)
TJITTER (tJC)
DUTY CYCLE (tD)
THSKW (tSK)
THSTB (fST)
PARAMETER
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK rise time
CPUCLK fall time
CPUCLK jitter
Output Duty Cycle
CPU Bus CLK skew
CPUCLK stabilization from Power-up
TEST CONDITIONS
66MHz
100MHz
NOTES
2
1, 5
1, 5
2
1, 5
1, 5
9
9
1
2
7
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
15.0
15.5
5.2
5.0
10.0
10.5
3.0
2.8
0.4
1.6
0.4
1.6
175
45
55
175
3
UNIT
ns
ns
ns
ns
ps
%
ps
ms
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)
SYMBOL
TPKP (tP)
TPKPS
TPKH (tH)
TPKL (tL)
THRISE (tR)
THFALL (tF)
TPSKW (tSK)
THPOFFSET (tO)
TPSTB (fST)
PARAMETER
PCICLK period
PCICLK period stability
PCICLK HIGH time
PCICLK LOW time
PCICLK rise time
PCICLK fall time
PCI Bus CLK skew
CPUCLK to PCICLK Offset
PCICLK stabilization from Power-up
TEST CONDITIONS
NOTES
3
8
1
1
10
10
2
2, 4
7
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
30.0
500
12.0
12.0
0.5
2.0
0.5
2.0
500
1.5
4.0
3
UNIT
ns
ps
ns
ns
ns
ns
ps
ns
ms
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
SYMBOL
f
THRISE (tR)
THFALL (tF)
DUTY CYCLE (tD)
THSTB (fST)
PARAMETER
Frequency, Actual
Output rise edge rate
Output fall edge rate
Duty Cycle
Frequency stabilization from Power-up (cold start)
TEST CONDITIONS
NOTES
Frequency generated
by Crystal
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
14.31818
1
4
1
4
45
55
3
UNIT
MHz
ns
ns
%
ms
1998 Sep 29
8
Share Link: 