PCK2000DL Просмотр технического описания (PDF) - Philips Electronics
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PCK2000DL Datasheet PDF : 14 Pages
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Philips Semiconductors
CK97 (66/100MHz) System Clock Generator
Product specification
PCK2000
BLOCK DIAGRAM
XTAL_IN X
XTAL_OUT X
14.318
MHZ
OSC
PWRDWN
LOGIC
PLL2
PLL1
PWRDWN
LOGIC
STOP
LOGIC
X REFCLK [0–2](14.318 MHz)
X IOAPIC [0–1](14.318 MHz)
X 48MHz [0–1](48MHz)
X CPUCLK [0–3] (100MHz/66MHz)
SEL0 X
SEL1 X
SEL100/66 X
LOGIC
CPUSTOP X
PCISTOP X
PWRDWN X
PWRDWN
LOGIC
STOP
LOGIC
X PCICLK_F (33MHz)
X PCICLK [1–7](33MHz)
SW00236
SELECT FUNCTIONS
SEL100/66
SEL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
NOTE:
1. Internal decode logic for all three select inputs implemented.
SEL0
0
1
0
1
0
1
0
1
FUNCTION
TRI-State
Reserved
Reserved
Active 66MHz
Test mode
Reserved
Reserved
Active 100MHz
FUNCTION
DESCRIPTION
3-STATE
TEST MODE
CPU
HI-Z
TCLK/2
PCI, PCI_F
HI-Z
TCLK/6
OUTPUTS
48MHz
REF
HI-Z
HI-Z
TCLK/2
TCLK
NOTE:
1. TCLK is a test clock driven in on the XTAL_IN input in Test Mode.
IOAPIC
HI-Z
TCLK
NOTES
1
1
NOTES
1998 Sep 29
4
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