AD9750 Просмотр технического описания (PDF) - Analog Devices

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AD9750

10-Bit, 125 MSPS High Performance TxDAC® D/A Converter

Analog Devices 

PIN CONFIGURATION

(MSB) DB9 1

28 CLOCK

DB8 2

27 DVDD

DB7 3

26 DCOM

DB6 4

25 NC

DB5 5

24 AVDD

AD9750

DB4 6 TOP VIEW 23 ICOMP

DB3 7 (Not to Scale) 22 IOUTA

DB2 8

21 IOUTB

DB1 9

20 ACOM

DB0 10

19 NC

NC 11

18 FS ADJ

NC 12

17 REFIO

NC 13

16 REFLO

NC 14

15 SLEEP

NC = NO CONNECT

AD9750

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

1

2–9

10

11–14, 19, 25

15

DB9

DB8–DB1

DB0

NC

SLEEP

16

REFLO

17

REFIO

18

FS ADJ

20

ACOM

21

IOUTB

22

IOUTA

23

ICOMP

24

AVDD

26

DCOM

27

DVDD

28

CLOCK

Description

Most Significant Data Bit (MSB).

Data Bits 1–8.

Least Significant Data Bit (LSB).

No Internal Connection.

Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated

if not used.

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal

reference.

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO

to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to

ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.

Full-Scale Current Output Adjust.

Analog Common.

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

Analog Supply Voltage (+4.5 V to +5.5 V).

Digital Common.

Digital Supply Voltage (+2.7 V to +5.5 V).

Clock Input. Data latched on positive edge of clock.

REV. 0

–5–

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