AD9750 Просмотр технического описания (PDF) - Analog Devices

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AD9750

10-Bit, 125 MSPS High Performance TxDAC® D/A Converter

Analog Devices 

AD9750

REFERENCE OPERATION

The AD9750 contains an internal 1.20 V bandgap reference

that can easily be disabled and overridden by an external refer-

ence. REFIO serves as either an input or output depending on

whether the internal or an external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 18, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1 µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external

amplifier having an input bias current less than 100 nA if any

additional loading is required.

OPTIONAL

EXTERNAL

REF BUFFER

ADDITIONAL

LOAD

0.1␮F

2k⍀

+5V

REFLO

+1.2V REF

REFIO

FS ADJ

AD9750

150pF

AVDD

CURRENT

SOURCE

ARRAY

Figure 18. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 19. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input im-

pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

AVDD

AVDD

EXTERNAL

REF

VREFIO

REFLO

+1.2V REF

REFIO

FS ADJ

RSET IREF =

VREFIO/RSET

AD9750

150pF

AVDD

CURRENT

SOURCE

ARRAY

REFERENCE

CONTROL

AMPLIFIER

Figure 19. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9750 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, IOUTFS.

The control amplifier is configured as a V-I converter as shown

in Figure 19, such that its current output, IREF, is determined by

the ratio of the VREFIO and an external resistor, RSET, as stated

in Equation 4. IREF is copied over to the segmented current

sources with the proper scaling factor to set IOUTFS as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5 µA and 625 µA. The wide adjustment span of IOUTFS

provides several application benefits. The first benefit relates

directly to the power dissipation of the AD9750, which is

proportional to IOUTFS (refer to the Power Dissipation section).

The second benefit relates to the 20 dB adjustment, which is

useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 0.5 MHz. The output of the control amplifier is

internally compensated via a 150 pF capacitor that limits the

control amplifier small-signal bandwidth and reduces its

output impedance. Since the –3 dB bandwidth corresponds to

the dominant pole, and hence the time constant, the settling

time of the control amplifier to a stepped reference input re-

sponse can be approximated. In this case, the time constant can

be approximated to be 320 ns.

There are two methods in which IREF can be varied for a fixed

RSET. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode

voltage of REFIO is varied over its compliance range of 1.25 V

to 0.10 V. REFIO can be driven by a single-supply amplifier or

DAC, thus allowing IREF to be varied for a fixed RSET. Since the

input impedance of REFIO is approximately 1 MΩ, a simple,

low cost R-2R ladder DAC configured in the voltage mode

topology may be used to control the gain. This circuit is shown

in Figure 20 using the AD7524 and an external 1.2 V reference,

the AD1580.

The second method may be used in a dual-supply system in

which the common-mode voltage of REFIO is fixed and IREF is

varied by an external voltage, VGC, applied to RSET via an ampli-

fier. An example of this method is shown in Figure 21, in which

the internal reference is used to set the common-mode voltage

of the control amplifier to 1.20 V. The external voltage, VGC, is

referenced to ACOM and should not exceed 1.2 V. The value of

RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA

AVDD

1.2V

AD1580

AVDD

REFLO

RFB

VDD

OUT1

AD7524

OUT2

VREF

AGND

DB7–DB0

0.1V TO 1.2V

RSET

IREF =

VREF/RSET

+1.2V REF

REFIO

FS ADJ

AD9750

150pF

Figure 20. Single-Supply Gain Control Circuit

AVDD

CURRENT

SOURCE

ARRAY

–10–

REV. 0

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