AD9070(RevB) Просмотр технического описания (PDF) - Analog Devices

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AD9070
(Rev.:RevB)

10-Bit, 100 MSPS A/D Converter

Analog Devices 

AD9070

APPLICATION NOTES

Theory of Operation

The AD9070 employs a two-step subranging architecture with

digital error correction.

The sampling and conversion process is initiated by a rising

edge at the ENCODE input. The analog input signal is

buffered by a high speed differential amplifier and applied to a

track-and-hold (T/H) circuit that captures the value of the

input at the sampling instant and maintains it for the duration

of the conversion.

The coarse quantizer (ADC) produces a five-bit estimate of the

input value. Its digital output is reconverted to analog form by

the reconstruction DAC and subtracted from the input signal in

the SUM AMP. The second stage quantizer generates a six-bit

representation of the difference signal. The eleven bits are

presented to the ENCODE LOGIC, which corrects for range

overlap errors and produces an accurate ten-bit result.

Data are strobed to the output on the rising edge of the ENCODE

input, with the data from sample N appearing on the output

following ENCODE rising edge N+3.

USING THE AD9070

ENCODE Input

Any high speed A/D converter is extremely sensitive to the quality

of the sampling clock provided by the user. A Track/Hold circuit is

essentially a mixer, and any noise, distortion or timing jitter on

the clock will be combined with the desired signal at the A/D

output. For that reason, considerable care has been taken in the

design of the ENCODE input of the AD9070 and the user is

advised to give commensurate thought to the clock source.

The ENCODE input is fully differential and may be operated in

a differential or a single-ended mode. It has a common-mode

range of –1 V to –3 V, and is easily driven by a differential ECL

driver. Proper termination at the A/D is important.

–5V

CLKIN

(1Vp-p)

0.1␮F

RT

10k⍀

0.1␮F 1k⍀ 3k⍀

VEE GND

AD9070

ENCODE

ENCODE

–5V

Figure 17. Single-Ended ENCODE: AC Coupled

In single-ended mode, the ENCODE input must be tied to an

appropriate reference voltage, generally midway between the

high and the low levels of the incoming logic signal. Many ECL

circuits provide a VBB reference voltage intended for this

purpose. If a reference voltage is produced by dividing the

power supply voltage, any noise on the supply used will couple

to the clock input and then to the output data. This is not

recommended. A better approach is to develop the required

voltage from the internal or external converter voltage reference

(VREF OUT).

Very small timing errors can reduce the performance of an A/D

dramatically. Total jitter of only 3.2 ps will limit the perfor-

mance of an A/D sampling a full-scale 50 MHz signal to nine

effective bits. The AD9070’s specified aperture jitter of 2.5 ps

leaves only 2.0 ps of jitter budget for the clock source (an RSS

calculation).

The cleanest clock source is only a crystal oscillator producing a

pure sine wave. In this configuration, or with any roughly

symmetrical clock input, the input can be ac coupled and biased

to a reference voltage that also provides the ENCODE input

(Figure 17). This ensures that the reference voltage is centered

on the ENCODE signal.

Digital Outputs

The digital outputs are compatible with 10K ECL logic. The

suggested pull-down is 100 Ω to –2 V. However, to reduce

power consumption, higher value pull-down resistors can be

used when driving very low capacitance loads or at reduced

encode rates. The falling edge slew rate of the output bits will be

degraded with higher value pull-down resistors.

Analog Input

The analog input to the AD9070 is a differential amplifier, but

the design has been optimized for a single-ended input. The

AIN input should be connected or bypassed to the ground

reference of the input signal. For best dynamic performance,

impedances at AIN and AIN should match.

The circuit in Figure 18 illustrates a simple ac-coupled inter-

face. The midscale input voltage and the AIN levels are both

provided by the internal reference (VREF OUT).

VIN

1Vp-p

0.1␮F

RT

500⍀

500⍀

0.1␮F

GND

AIN AD9070

AIN

(MSB) D9

VREF OUT

VREF IN

D9

510⍀

(OR 100⍀ TO –2V)

–5V

ENCODE

ENCODE

ENCODE (LSB) D0

ENCODE

REF

COMP VEE BYPASS

D0

510⍀

(OR 100⍀ TO –2V)

–5V

0.1␮F

0.1␮F

–5V

Figure 18. AD9070 in –5 V (ECL) Environment

REV. B

–9–

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