MX844 Просмотр технического описания (PDF) - IXYS CORPORATION
Номер в каталоге
Компоненты Описание
производитель
MX844 Datasheet PDF : 21 Pages
| |||
MX844
IXYS
REGISTER ADDRESS AND BIT ASSIGNMENT
All registers are read/write except for the two ADC result registers which are read only. The left hand
column refers to the data bits shown as B7 through B0 on the synchronous serial I/O timing diagram.
CONTROL REGISTER, address A[2:0] = 000 binary
CR[7:5] Clock divisor
ADC Clock divisor
bits M1 low M1 high
000
8
8
001
4
4
010
6
12
011
3
13
100 192
160
101 216
180
110 288
240
111 312
260
Baud rate divisor
M1 low M1 high
512 416
256 208
384 768
192 832
1024 1024
1152 1152
1536 1536
1664 1664
CR[4:3] Input channel select
00 IN1
01 IN3
10 GND
11 IN2
CR[2:0] Full scale select
V(INxP) – V(INxN)
000 +/- 50 mV
001 +/- 25 mV
010 +/- 250 mV
011 +/- 10 mV
100 0 to 100 mV
101 0 to 50 mV
110 selects the internal temperature sensor
111 0 to 20 mV
COMP_1 REGISTER, A[2:0] = 001 binary
7:0
Eight least significant bits of comparator 1
COMP_2 REGISTER, A[2:0] = 010 binary
7:0
Eight least significant bits of comparator 2
COMP_MSN REGISTER, A[2:0] = 011 binary
7:4
Four most significant bits of comparator 1
3:0
Four most significant bits of comparator 2
MX844
Drawing No. 084423
8
08/25/06
www.claremicronix.com
Share Link: 