MX7534 Просмотр технического описания (PDF) - Maxim Integrated
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MX7534 Datasheet PDF : 16 Pages
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Microprocessor-Compatible,
14-Bit DACs
R1
VIN
100Ω VDD
A0 16
A1 15
CS 18
1 19 2 R2
REF
RFB 33Ω
MX7534
3
IOUT
AGNDS 4
C1
33pF
A1
WR 17
AGNDF 5
VO
D7–D0 DGND VSS
7–14
6
20
INPUT
DATA
ANALOG
GROUND
Figure 4a. Unipolar Binary Operation
R1
R2
20Ω
10Ω
VIN
2
1 26 3
C1
LDAC 23
CSMSB 22
25
WR
REFF REFS VDD RFB
4
IOUT
MX7535
AGNDS 5
33pF
A1
24
CSLSB
AGNDF 6
VO
D13–DO DGND VSS
8–21
7
27
INPUT
DATA
ANALOG
GROUND
Figure 4b. Unipolar Binary Operation
Grounding Considerations
Since IOUT and the output amplifier noninverting input
are sensitive to offset voltages, connect nodes that
must be grounded directly to a single-point ground
through a separate, very-low-resistance path. Note that
the output currents at IOUT and AGNDF vary with input
code and create code-dependent error if these termi-
nals are connected to ground (or a virtual ground)
through a resistive path.
To obtain high accuracy, it is important to use a proper
grounding technique. The two AGND pins (AGNDF‚
AGNDS) provide flexibility in this respect. In Figures 4a
and 4b, AGNDS and AGNDF are shorted together
externally and an extra op amp, A2, is not used.
Voltage-drops due to bond-wire resistance are not
compensated for in this circuit; this could create a lin-
earity error of approximately 0.1LSB due to bond-wire
resistance alone. This can be eliminated by using the
circuits shown in Figures 6a and 6b, where A2 main-
tains AGNDS at signal ground potential. By using
force/sense techniques, all switch contacts on the DAC
are kept at exactly the same potential, and any error
caused by bond-wire resistance is eliminated.
Figure 7 shows a remote voltage reference driving the
MX7535. Op amps A2 and A3 compensate for voltage
drops along the reference input line and analog
ground line.
Figure 8 shows a printed circuit board (PCB) layout with
a single output amplifier for the MX7534. The input to
REF (Pin 1) is shielded to reduce AC feedthrough, while
the digital inputs are shielded to minimize digital
Table 2. Unipolar Binary Code Table
BINARY NUMBER IN
DAC REGISTER
MSB
11 1111
1111
LSB
1111
10 0000
0000 0000
00 0000
0000 0001
00 0000
0000 0000
ANALOG OUTPUT
(VOUT)
( ) -VIN
16383
16384
( ) -VIN
8192
16384
=
-
1
2
VIN
( ) -VIN
1
16384
0V
feedthrough. The traces connecting IOUT and AGNDS
to the inverting and noninverting op amp inputs are
kept as short as possible. Gain trim components, R3
and R4, are omitted.
Zero-Offset Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 0s.
2) Adjust offset of amplifier A2 for minimum potential at
AGNDS. This potential should be ≤30µV with respect
to signal ground.
3) Adjust A1’s offset so that VOUT is at a minimum
(i.e., ≤30µV).
8 _______________________________________________________________________________________
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