MX26L6419 Просмотр технического описания (PDF) - Macronix International

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MX26L6419

64M [x16] SINGLE 3V PAGE MODE MTP MEMORY

Macronix International 

MX26L6419

Figure 1. Block Architecture

MTP memory reads erases and writes in-system via the local CPU. All bus cycles to or from the MTP memory

conform to standard microprocessor bus cycles.

A21~A0

3FFFFF

3F0000

1FFFFF

1F0000

01FFFF

010000

00FFFF

000000

64-Kword Block

63

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.

.

64-Kword Block

31

.

.

.

64-Kword Block

1

64-Kword Block

0

Word Mode (x16)

P/N:PM0946

REV. 0.3, OCT. 08, 2003

4

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