TQ8033 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ8033 Datasheet PDF : 18 Pages
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TQ8033
DATA SHEET
Circuit Description
Data Inputs
The 64 data input channels are differential PECL
compatible. All inputs have a 2.5KΩ Thevenin
equivalent bias circuit which holds the DC bias at
VDD-1.3 Volts simplifying the design of applications
requiring AC coupling. Input signals must be properly
terminated for maximum performance. Terminate one
side (true or complement) of any unused inputs to VTT .
Data Outputs
The 33 data output channels are differential PECL
compatible and designed to be terminated to 50Ω to
VDD -2.0 Volts. Unused outputs can be left
unterminated if desired in order to save power.
Control Inputs
To program the TQ8033, the address of the desired
output port is applied to the inputs (OADD0:4; where
00000=O0 and 11111=O31). The address of the desired
input port is applied to the inputs (IADD0:5; where
000000=I0 and 111111=I63).
The new configuration is loaded into the program
registers by asserting the LOAD signal high. The data
is latched when LOAD is de-asserted. LOAD should
remain low and only be asserted for the time necessary
to load the new configuration data.
The process is repeated for each output port
configuration. Only the output ports which are to
receive a new input port configuration need to be
programmed. The new configurations are not applied
to the switch core at this time and there is no
disruption of the data flowing through the switch core.
The control inputs interface levels are TTL compatible.
Program Registers
The configuration data for each of the 33 data channels
have two sets, or stages, of configuration storage
registers. The first stage, known as the program
register, stores a new set of input configurations prior
to application to the switch core. The second stage,
known as the configuration register, stores the current
switch core configurations.
The use of two stage configuration storage registers
allows new input configurations to be loaded without
disturbing the existing configuration. After the new
input configurations have been loaded into the program
registers, the CONFIGURE input is asserted and the
new configurations are applied to the switch core.
After the new configurations have been loaded into the
program registers, the CONFIGURE input is asserted
and the data in the program registers is loaded into the
configuration registers. The data is latched on the
falling edge of CONFIGURE.
The switch core receives the new configuration as soon
as CONFIGURE is asserted. During the time the new
configurations are being applied to the switch core, the
integrity of the data on output ports which receive a
new configuration is unknown for a period of tdcf from
the time CONFIGURE is asserted.
If desired, the LOAD and CONFIGURE can be asserted
simultaneously. In this mode, the new configuration
will be applied to the switch core when LOAD is
asserted.
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