DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

NT5SV16M4DT Просмотр технического описания (PDF) - Nanya Technology

Номер в каталоге
Компоненты Описание
производитель
NT5SV16M4DT
Nanya
Nanya Technology Nanya
NT5SV16M4DT Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
NT5SV16M4DT
NT5SV8M8DT
NT5SV4M16DT
64Mb Synchronous DRAM
Current State Truth Table (Part 2 of 3)(See note 1)
Command
Current State
CS RAS CAS WE BS0,BS1 A11 - A0
Description
Action
Notes
LLLL
OP Code
Mode Register Set ILLEGAL
L L LH
X
X
Auto or Self Refresh ILLEGAL
LLHL
BS
X
Precharge
ILLEGAL
4
Read with
L LHH
BS Row Address Bank Activate
ILLEGAL
4
Auto Pre-
LHL L
BS
Column Write
ILLEGAL
4
charge
LHLH
BS
Column Read
ILLEGAL
4
L HH L
X
X
Burst Termination ILLEGAL
L HHH
X
X
No Operation
Continue the Burst
HXXX
X
X
Device Deselect
Continue the Burst
LLLL
L L LH
OP Code
X
X
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
LLHL
BS
X
Precharge
ILLEGAL
4
L LHH
BS Row Address Bank Activate
ILLEGAL
4
Write with Auto
Precharge
L
H
L
L
BS
Column Write
ILLEGAL
4
LHLH
BS
Column Read
ILLEGAL
4
L HH L
X
X
Burst Termination ILLEGAL
L HHH
X
X
No Operation
Continue the Burst
HXXX
X
X
Device Deselect
Continue the Burst
LLLL
OP Code
Mode Register Set ILLEGAL
L L LH
X
X
Auto or Self Refresh ILLEGAL
LLHL
BS
X
Precharge
No Operation; Bank(s) idle after tRP
L LHH
BS Row Address Bank Activate
ILLEGAL
4
Precharging L H L L
BS
Column Write
ILLEGAL
4
LHLH
BS
Column Read
ILLEGAL
4
Row
Activating
L HH L
L HHH
HXXX
LLLL
L L LH
LLHL
L LHH
LHL L
LHLH
L HH L
L HHH
HXXX
X
X
Burst Termination
X
X
No Operation
X
X
Device Deselect
OP Code
Mode Register Set
X
X
Auto or Self Refresh
BS
X
Precharge
BS Row Address Bank Activate
BS
Column Write
BS
Column Read
X
X
Burst Termination
X
X
No Operation
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Row Active after tRCD
No Operation; Row Active after tRCD
No Operation; Row Active after tRCD
4
4, 10
4
4
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
REV 1.1
10/01
11
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]