NM25C640 Просмотр технического описания (PDF) - Fairchild Semiconductor

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NM25C640

64K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)

Fairchild Semiconductor 

Functional Description (Continued)

WRITE SEQUENCE: To program the device, the WRITE PRO- At the completion of a WRITE cycle the device is automatically

TECT (WP) pin must be held high and two separate instructions returned to the write disable state.

must be executed. The chip must first be write enabled via the

WRITE ENABLE instruction and then a WRITE instruction must

be executed. Moreover, the address of the memory location(s) to

be programmed must be outside the protected address field

selected by the Block Write Protection Level. See Table 3.

If the device is not WRITE enabled, the device will ignore the

WRITE instruction and return to the standby state when CS is

forced high. A new CS falling edge is required to re-initialize the

serial communication.

A WRITE command requires the following sequence. The CS line

is pulled low to select the device, then the WRITE op-code is

transmitted on the SI line followed by the high order address byte

(A12-A8) and the low order address byte (A7–A0). The leading

five bits in the high order address byte will be ignored. The address

is followed by the data (D7–D0) to be written. Programming will

start after the CS pin is forced back to a high level. Note that the

WRITE STATUS REGISTER (WRSR): The WRITE STATUS

REGISTER (WRSR) instruction is used to program the non-

volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE

PROTECT (WP) pin must be held high and two separate instruc-

tions must be executed. The chip must first be write enabled via

the WRITE ENABLE instruction and then a WRSR instruction

must be executed.

LOW to HIGH transition of the CS pin must occur during the SCK

low time immediately after clocking in the D0 data bit. See Figure

10.

The WRSR command requires the following sequence. The CS

line is pulled low to select the device and then the WRSR op-code

is transmitted on the SI line followed by the data to be pro-

FIGURE 10. End of WRITE Sequence

grammed. See Figure 12.

 CS

SCK

SI D2

D1

D0

SO

DS500041-12

The READY/BUSY status of the device can be determined by

FIGURE 12. Write Status Register

CS

SI

WRSR

SR Data

Op-Code xxxxBP1BP0xx

SO

DS500041-14

Note that the first four bits are don’t care bits followed by BP1 and

executing a READ STATUS REGISTER (RDSR) instruction. Bit 0 BP0 then two additional don’t care bits. Programming will start

= 1 indicates that the WRITE cycle is still in progress and Bit 0 = after the CS pin is forced back to a high level. As in the WRITE

0 indicates that the WRITE cycle has ended. During the WRITE instruction the LOW to HIGH transition of the CS pin must occur

programming cycle (Bit 0 = 1) only the READ STATUS REGIS- during the SCK low time immediately after clocking in the last don’t

TER instruction is enabled.

care bit. See Figure 13.

The NM25C640 is capable of a 32 byte PAGE WRITE operation. FIGURE 13. Start WRSR Condition

After receipt of each byte of data the five low order address bits are

internally incremented by one. The eight high order bits of the

CS

  addresswillremainconstant.Ifthemastershouldtransmitmore

than 32 bytes of data, the address counter will “roll over,” and the

previously loaded data will be reloaded. See Figure 11.

FIGURE 11. 32 Byte Page Write

CS

SCK

SI

BP0

SI

Write Byte H Byte L Data Data Data Data

Op-Code Addr (n) Addr (n) (n) (n+1) (n+2) (n+3)

. . . Data

(n+31)

SO

SO

DS500041-15

The READY/BUSY status of the device can be determined by

executing a READ STATUS REGISTER (RDSR) instruction. Bit 0

= 1 indicates that the WRSR cycle is still in progress and Bit 0 =

DS500041-13

0 indicates that the WRSR cycle has ended.

At the completion of a WRITE cycle the device is automatically

returned to the write disable state.

NM25C640 Rev. D.2

8

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