MT91L62 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT91L62

3 Volt Single Rail Codec

Zarlink Semiconductor Inc 

MT91L62

Data Sheet

Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT91L62 will re-align

its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,

CSL1 and CSL0 are used to program the bit rates.

For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the

STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.

Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during

the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.

For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed

output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation

since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM

serial circuit for asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and

asynchronous SSI timing.

PWRST

While the MT91L62 is held in PWRST no device control or functionality is possible.

Serial Port

PCM

Din

Decoder

Filter/Codec and Analog Interface

Default Bypass

Receive

Filter Gain

0 dB

0 dB

Receiver

Driver

Aout +

Aout-

20kΩ

PCM

Dout

Encoder

Transmit Gain

6 dB

Internal To Device

Figure 3 - Audio Gain Partitioning

AIN+ Analog

Input

AIN-

External To Device

5

Zarlink Semiconductor Inc.

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