MT91L62 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT91L62 Datasheet PDF : 19 Pages
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MT91L62
Data Sheet
Analog Interfaces
Standard interfaces are provided by the MT91L62. These are:
• The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 2.123 Vpp µ−law
across AIN+/AIN- and 2.2 Vpp A-law across these pins.
• The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output
driver is capable of driving a load of 20 k ohms.
PCM Serial Interface
A serial link is required to transport data between the MT91L62 and an external digital transmission device. The
MT91L62 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI).
The bit clock rate is selected by setting the CSL2-0 control pins as shown in Figure 2.
Quiet Code
The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute
pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the TxMute pin is high. When
either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet
code definition.
CSL2
1
1
0
0
0
0
CSL1
CSL0
External Clock
Bit Rate (kHz)
CLOCKin
(kHz)
0
0
0
1
0
0
0
1
1
0
1
1
128
256
512
1536
2048
4096
4096
4096
512
1536
2048
4096
Table 2 - Bit Clock Rate Selection
SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if
the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.
In SSI mode the MT91L62 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel
data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT91L62 functions allowing synchronous operation. If the
available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal
MT91L62 functions.
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Zarlink Semiconductor Inc.
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