MT9162AN1 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9162AN1

ISO2-CMOS 5 Volt Single Rail Codec

Zarlink Semiconductor Inc 

MT9162

Data Sheet

Pin Description (continued)

Pin # Name

Description

16 AOUT- Inverting Analog Output. (balanced).

17 AOUT+ Non-Inverting Analog Output. (balanced).

18

VSS Ground. Nominally 0 volts.

19

Ain- Inverting Analog Input. No external anti-aliasing is required.

20

Ain+ Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.

Overview

The 5 V single rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals

(Filter/Codec) and an analog interface to a standard analog transmitter and receiver (Analog Interface). The

receiver amplifier is capable of driving a 20 k ohm load.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain

compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are

programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion.

The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the

nominal half-channel for the MT9162.

The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide

dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the analog

interface section to provide full chip realization of these capabilities for the external functions.

A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for

biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it

may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog

ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the VRef pin to

ground is required at all times. The analog ground reference point for these two capacitors must be physically the

same point. To facilitate this the VRef and VBias pins are situated on adjacent pins.

The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second

order lowpass implementation with a corner frequency at 25 kHz.

The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the

sinx/x attenuation caused by the 8 kHz sampling rate.

Companding law selection for the Filter/Codec is provided by the A/ µ companding control pin. Table 1 illustrates

these choices.

3

Zarlink Semiconductor Inc.

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