MT9196 Просмотр технического описания (PDF) - Mitel Networks

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MT9196

ISO2-CMOS Integrated Digital Phone Circuit (IDPC)

Mitel Networks 

MT9196

Preliminary Information

IDPC. During a valid read transfer from IDPC data

simultaneously clocked out by the micro is ignored

by IDPC.

All data transfers through the microport are two-byte

transfers requiring the transmission of a Command/

Address byte followed by the data byte written or

read from the addressed register. CS must remain

asserted for the duration of this two-byte transfer. As

shown in Figures 5 and 6 the falling edge of CS

indicates to the IDPC that a microport transfer is

about to begin. The first 8 clock cycles of SCLK after

the falling edge of CS are always used to receive the

Command/Address byte from the microcontroller.

The Command/Address byte contains information

detailing whether the second byte transfer will be a

read or a write operation and at what address. The

next 8 clock cycles are used to transfer the data byte

COMMAND/ADDRESS 

Œ

DATA INPUT/OUTPUT

Œ

 COMMAND/ADDRESS:

DATA 1

RECEIVE

D0

D1

D2

D3

D4

D5

D6

D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

DATA 1

TRANSMIT

SCLK y

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

CS



Ž

Ž

ΠDelays due to internal processor timing which are transparent to IDPC.

y The IDPC:- latches received data on the rising edge of SCLK.

- outputs transmit data on the falling edge of SCLK.

Ž The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

 A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

 The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

5 bits - Addressing Data

2 bits - Unused

D7

D0

X

X A4 A3 A2 A1 A0 R/W

Figure 5 - Serial Port Relative Timing for Intel Mode 0

COMMAND/ADDRESS  Œ

DATA INPUT/OUTPUT

Œ

 COMMAND/ADDRESS:

DATA 2

RECEIVE

D7

D6

D5

D4

D3

D2

D1

D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

DATA 1

TRANSMIT

SCLK y

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

CS



Ž

Ž

ΠDelays due to internal processor timing which are transparent to IDPC.

y The IDPC:- latches received data on the rising edge of SCLK.

- outputs transmit data on the falling edge of SCLK.

Ž The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

 A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

 The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

5 bits - Addressing Data

2 bits - Unused

D7

R/W X

D0

A4 A3 A2 A1 A0 X

Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

7-136

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