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MT91610

Analog Ringing SLIC

Mitel Networks 

MT91610

Preliminary Information

Impedance Programming

Loop Supervision

The MT91610 allows the designer to set the device’s

impedance across TIP and RING, (ZTR), and

network balance impedance, (ZNB), separately with

external low cost components.

The impedance (ZTR) is set by R4, R5, whilst the

network balance, (ZNB), is set by R6, R8, (see Figure

4.)

The network balance impedance should be

calculated once the 2W - 4W gain has been set.

Line Impedance

For optimum performance, the characteristic

impedance of the line, (Zo), and the device’s

impedance across TIP and RING, (ZTR), should

match. Therefore:

Zo = ZTR

The relationship between Zo and the components

that set ZTR is given by the formula:

Zo / ( Ra+Rb) = kZo / R4

where kZo = R5

Ra = Rb

The value of k can be set by the designer to be any

value between 20 and 250. R4 and R5 should be

greater than 50kΩ.

Network Balance Impedance

The network balance impedance, (ZNB), will set the

transhybrid loss performance for the circuit. The

transhybrid loss of the circuit depends on both the 4 -

2 Wire gain and the 2 - 4 Wire gain.

The method of setting the values for R6 (or Z6... it

can be a complex impedance) is given as below:

R6 = R7 * (R9 / R10) * 2.2446689 * ( ZNB / ZNB + Zo)

Please note that in the case of Zo not equal to ZNB

(the THL compromized case) R6 is a complex

impedance. In the general case of Zo matches to ZNB

(the THL optimized case) R6 is just a single resistor.

The Loop Supervision circuit monitors the state of

the phone line and when the phone goes "Off Hook"

the SHK pin goes high to indicate this state. This pin

reverts to a low state when the phone goes back "On

Hook" or if the loop resistance is too high (>2.3KΩ)

When loop disconnect dialing is being used, SHK

pulses to logic 0 indicate the digits being dialled.

This output should be debounced.

Constant Current Control & Voltage

Fold Over Mode

The SLIC employs a feedback circuit to supply a

constant feed current to the line. This design is

accomplished by sensing the sum of the voltages

across the feed resistors, Ra and Rb, and comparing

it to the input reference voltage, Vref, that

determines the constant current feed current.

By using a resistive divider network, (Figure 3), it is

possible to generate the required voltage to set the

ILOOP. This voltage can be calculated by the formula:

ILOOP = [ G * 5] * 3

(Ra +Rb)

where, G = R2 / (R1 + R2)

ILOOP is in Ampere.

R1= 200KΩ

From Figure 3 with Ra = Rb = 100 Ω

For ILOOP = 20mA, R2 = 72.73 KΩ

For ILOOP = 25mA, R2 = 100 KΩ

For ILOOP = 30mA, R2 = 133.33 KΩ

R2

**kΩ

6 VREF

C2

0.1uF

R1

200K MT91610

+5V

** See Figure 6

Figure 3 - Loop Setting

For convenience, a graph which plots the value of

R2 (KΩ) versus the expected loop current is shown

in Figure 6.

4

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