MT9076 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT9076

T1/E1/J1 3.3 V Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9076B

Data Sheet

Microprocessor Port

The MT9076 registers are accessible via an 8-bit parallel Motorola or Intel non-multiplexed microprocessor

interface.

LIU

The MT9076 LIU interfaces the digital framer functions to either the DS1 (T1 mode) or PCM 30 (E1 mode)

transformer-isolated four wire line.

In T1 mode, the LIU can pre-equalize the transmit signal to meet the T1.403 and T1.102 pulse templates after

attenuation by 0 - 655 feet of 22 AWG PIC cable, alternatively it can provide line build outs of 7.5 dB, 15 dB and

22.5 dB. In T1 mode the receiver can recover signals attenuated by up to 36 dB at 772 kHz.

In E1 mode, the LIU transmits signals that meet the G.703 2.048 Mbit/s pulse template and the receiver can recover

signals attenuated by up to 40 dB at 1024 kHz.

Digital Framer Only Mode

To accommodate some special applications, the MT9076 supports a digital framer only mode that provides direct

access to the transmit and receive data in digital format, i.e., by-passing the analog LIU front-end. In digital framer

only mode, the MT9076 supports unipolar non-return to zero or bipolar return to zero data.

PLL and Slip Buffers

The MT9076 PLL attenuates jitter from 2.5 Hz with a roll-off of 20 dB/decade. The intrinsic jitter is less than 0.02 UI.

The device can operate in one of three timing modes: System Bus Synchronous Mode, Line Synchronous Mode, or

Free-run Mode. In all three timing modes the low jitter output of the PLL provides timing to the transmit side of the

LIU.

In T1 mode, the receive and transmit paths both include two-frame slip buffers. The transmit slip buffer features

programmable delay and serves as a Jitter Attenuator (JA) FIFO and a rate converter between the ST-BUS and the

1.544 Mbit/s T1 line rate.

In E1 mode, the receive path includes a two-frame slip buffer and the transmit path contains a 128 bit Jitter

Attenuator (JA) FIFO with programmable depth.

Interface to the System Backplane

On the system side the MT9076 framers can interface to a 2.048 Mbit/s or 8.192 Mbit/s ST-BUS backplane.

There is an asynchronous mode for Inverse MUX for ATM (IMA) applications, this enables the framer to interface to

a 1.544 Mbit/s (T1) or 2.048 Mbit/s (E1) serial bus with asynchronous transmit and receive timing.

Framing Modes

The MT9076 framers operate in termination mode or transparent mode. In the receive transparent mode, the

received line data is channelled to the DSTo pin with arbitrary frame alignment. In the transmit transparent mode,

no framing or signaling is imposed on the data transmitted from the DSTi pin onto the line.

In T1 mode, the framers operate in any of the following framing modes: D4, Extended Superframe (ESF) or SLC-

96.

In E1 mode, the framers run three framing algorithms: basic frame alignment, signaling multiframe alignment and

CRC-4 multiframe alignment. The Remote Alarm Indication (RAI) bit is automatically controlled by an internal state

machine.

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Zarlink Semiconductor Inc.

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