MT9076BB1 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

Номер в каталоге

Компоненты Описание

производитель

MT9076BB1

T1/E1/J1 3.3 V Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9076B

Data Sheet

Function

Mode

Loopbacks

Transmit FAS

Transmit non-FAS

Transmit MFAS (CAS)

Data Link

CRC Interworking

signaling

ABCD Bit Debounce

Interrupts

RxMF Output

Error Insertion

HDLCs

Counters

Transmit Data

Table 15 - Reset Status (E1)

Status

Termination

Deactivated

Cn0011011

1/Sn1111111

00001111

Deactivated

Activated

CAS Registers

Deactivated

Masked

signaling Multiframe

Deactivated

Deactivated

Cleared

All Ones

6.0 Transmit Data All Ones (TxAO) Operation

The TxAO (Transmit all ones) pin allows the PRI interface to transmit an all ones signal under hardware control.

7.0 Data Link Operation

7.1 Data Link Operation in E1 Mode

In E1 mode, MT9076 has a user defined 4, 8, 12, 16 or 20 kbit/s data link for transport of maintenance and

performance monitoring information across the PCM 30 link. This channel functions using the Sa bits (Sa4~Sa8) of

the PCM 30 timeslot zero non-frame alignment signal (NFAS). Since the NFAS is transmitted every other frame - a

periodicity of 250 microseconds - the aggregate bit rate is a multiple of 4 kb/s. As there are five Sa bits

independently available for this data link, the bit rate will be 4, 8, 12, 16 or 20 kb/s, depending on the bits selected

for the Data Link (DL).

The Sa bits used for the DL are selected by setting the appropriate bits, Sa4~Sa8, to one in the Data Link Select

Word (page 01H, address 17H, bits 4-0). Access to the DL is provided by pins TxDLCLK, TxDL, RxDLCLK and

RxDL, which allow easy interfacing to an external controller.

Data to be transmit onto the line in the Sa bit position is clocked in from the TxDL pin (pin 65 in PLCC, pin 47 in

LQFP) with the clock TxDLCLK (pin 64 in PLCC, pin 46 pin LQFP). Although the aggregate clock rate equals the bit

rate, it has a nominal pulse width of 244 ns, and it clocks in the TxDL as if it were a 2.048 Mb/s data stream. The

clock can only be active during bit times 4 to 0 of the STBUS frame. The TxDL input signal is clocked into the

MT9076 by the rising edge of TxDLCLK. If bits are selected to be a part of the DL, all other programmed functions

for those Sa bit positions are overridden.

38

Zarlink Semiconductor Inc.

Share Link: