MT9075B Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

Номер в каталоге

Компоненты Описание

производитель

MT9075B

E1 Single Chip Transceiver

Zarlink Semiconductor Inc 

MT9075B

Data Sheet

Pin Description (continued)

Pin #

PLCC MQFP

Name

Description

60 48

TAIS

Transmit Alarm Indication Signal (Input). An active low on this input causes the

MT9075B to transmit an AIS (all ones signal) on TTIP and TRING pins. TAIS should be

set to high for normal data transmission.

61 57

LOS

Loss of Signal or Synchronization (Output). When high, and LOS/LOF (page 02H

address 13H bit 2) is zero, this signal indicates that the receive portion of the MT9075B

is either not detecting an incoming signal (bit LLOS on page 03H address 18H is one) or

is detecting a loss of basic frame alignment condition (bit SYNC on page 03H address

10H is one). If LOS/LOF=1, a high on this pin indicates a loss of signal condition.

62 58

59

IC Internal Connection. Tie to VSS (Ground) for normal operation.

NC No Connection. Leave open for normal operation.

63 60

IC Internal Connection. Tie to VSS (Ground) for normal operation.

64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated 2.048

Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data link data

(TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also be used to clock

DL data out of an external serial controller.

65 62

TxDL

Transmit Data Link (Input). An input serial stream of transmit data link data at 4, 8, 12,

16 or 20 kbit/s composed of 488ns-wide bit cells which are multiplexed into selected

national bits of the PCM 30 transmit signal.

66 63

BL/FR Bus or Line/Freerun (Input). If this pin is set to high, the MT9075B is in the System Bus

or Line Synchronous mode depending on the BS/LS pin. If low, the MT9075B is in the

free run mode.

67 64 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).

68 65 VSS Negative Power Supply (Input). Digital ground.

1-7,

NC No Connection. Leave open for normal operation.

25-31,

49-56,

75-82,

100

Device Overview

The MT9075B is an advanced PCM 30 framer with an on-chip Line Interface Unit (LIU) that meets or supports the

latest ITU-T Recommendations for PCM 30 and ISDN primary rate including G.703, G.704, G.706, G.775, G.796,

G.732, G.823 and I.431. It also meets or supports the layer 1 requirements of ETSI ETS 300 011, ETS 300 166,

ETS 300 233 and BS6450.

The Line Interface Unit (LIU) of the MT9075B interfaces the digital framer functions to the PCM 30 transformer-

isolated four wire line. The transmit portion of the MT9075B LIU consists of a digital buffer, a digital-to-analog

converter and a differential line driver. The receiver portion of the LIU consists of an input signal peak detector, an

optional two-stage equalizer, a smoothing filter, data and clock slicers and a clock extractor. The optional equalizer

allows for error free reception of data with a line attenuation of up to 20 dB.

The LIU also contains a Jitter Attenuator (JA), which can be configured to either the transmit or receive path. The

JA will attenuate jitter from 2.5 Hz and roll-off at a rate of 20 dB/decade. Its intrinsic jitter is less than 0.02 UI.

7

Zarlink Semiconductor Inc.

Share Link: