MT9075B Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT9075B Datasheet PDF : 102 Pages
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MT9075B
Data Sheet
MT9075B Access and Control
Register Access
The control and status of the MT9075B is achieved through a non-multiplexed parallel microprocessor port. The
parallel port may be configured for Motorola style control signals (by setting pin INT/MOT low) or Intel style control
signals (by setting pin INT/MOT high).
The controlling microprocessor gains access to specific registers of the MT9075B through a two step process. First,
writing to the internal Command/Address Register (CAR) selects one of the 18 pages of control and status registers
(CAR address: AC4 = 0, AC3-AC0 = don't care, CAR data D7 - D0 = page number). Second, each page has a
maximum of 16 registers that are addressed on a read or write to a non-CAR address (non-CAR: address AC4 = 1,
AC3-AC0 = register address, D7-D0 = data). Once a page of memory is selected, it is only necessary to write to the
CAR when a different page is to be accessed. See Figures 11 and 12 for timing requirements.
Please note that for microprocessors with read/write cycles less than 200 ns, a wait state or a dummy operation (for
C programming) between two successive read/write operations to the HDLC FIFO is required.
Table 5 associates the MT9075B control and status pages with access and page descriptions.
Page Address
D7 - D0
00000001 (01H)
00000010 (02H)
00000011 (03H)
00000100 (04H)
00000101 (05H)
00000110 (06H)
00000111 (07H)
00001000 (08H)
00001001 (09H)
00001010 (0AH)
00001011 (0BH)
00001100 (0CH)
00001101 (0DH)
00001110 (0EH)
00001111 (0FH)
00010000 (10H)
00010001 (11H)
00010010 (12H)
Register Description
Master
Control
Master
Status
Per Channel Transmit Signalling
Per Channel Receive Signalling
Per Time Slot
Control
1 Second Status
unused
HDLC0 Control and Status (TS 0)
HDLC1 Control and Status (TS 16)
Transmit National Bit Buffer
Receive National Bit Buffer
Tx message mode Buffer 0
Tx message mode Buffer 1
Rx message mode Buffer 0
Rx message mode Buffer 1
Table 5 - Register Summary
Processor
Access
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
ST-BUS
Access
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CSTi
CSTo
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ST-BUS Streams
The ST-BUS stream can also be used to access channel associated signalling nibbles. CSTo contains the received
channel associated signalling bits (e.g., ITU-T R1 and R2 signalling), and when control bit RPSIG (page 01H,
address 1AH) is set to 0, CSTi is used to control the transmit channel associated signalling. The DSTi and DSTo
streams contain the transmit and receive voice and digital data.
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