MT90401 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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производитель

MT90401

SONET/SDH System Synchronizer

Zarlink Semiconductor Inc 

MT90401

Data Sheet

Pin Description (continued)

Pin # Name

Description

22 E3/DS3 E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of

44.736 MHz for the C34/C44 pin, while a high selects a clock rate of 34.368 MHz. This pin

performs no function if the device is not in hardware mode.

23

SEC Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of four possible frequencies ( 8kHz,

1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the

input reference is based upon the MS1, MS2 and RSEL control inputs.

24

PRI Primary Reference (Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of four possible frequencies (8 kHz,

1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. In hardware mode the selection of the

input reference is based upon the MS1, MS2 and RSEL control inputs.

25

VSS2 Digital ground. 0 Volts

26

IC

Internal Connection. Leave unconnected

27

VSS3 Analog ground. 0 Volts

28

VDD2 Positive Analog Power Supply. Analog supply.

29

VDD Positive Power Supply. Digital supply.

30

C155N, LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52 MHz clock

31

C155P

32

VSS4 Digital ground. 0 Volts

33

VREF LVDS Reference Voltage (Input).

34

Tdo IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected.

35

Tms IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high.

36

Tclk IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high.

37

Trst IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low.

38

Tdi IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high.

39

FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four

possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI

and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1

(Address 00H - Read/Write).

40

FS1 Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four

possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI

and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1

(Address 00H - Read/Write).

41 PRIOOR Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that

the primary reference is off the PLL center frequency by more than 12 ppm. The

measurement is done on a 1 second basis using a signal derived from the 20 MHz clock

input on C20i. When the accuracy of the 20 MHz clock is ± 4.6 ppm, the effective out of

range limits of the PRIOOR signal will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.

42

C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.

43

C6

Clock 6.312 MHz (CMOS Output). This output is used for DS2 or J2 applications.

44

IC

Internal Connection. Tie low for normal operation.

4

Zarlink Semiconductor Inc.

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