MT90401 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90401 Datasheet PDF : 38 Pages
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MT90401
Data Sheet
Pin Description
Pin # Name
Description
1
IC
Internal Connection. Leave unconnected.
2-5 A1 - A4 Address 1 to 4 (5 V tolerant Inputs). Address inputs for the parallel processor interface.
6
VSS9 Digital ground. 0 Volts
7, 8 A5, A6 Address 5, to 6 (5 V tolerant Input). Address inputs for the parallel processor interface.
9 SONET/SD SONET/SDH (Input). In hardware mode set this pin high to have a loop filter corner
H
frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to
have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per
1.326 ms. This pin performs no function if the device is not in hardware mode.
10
VDD1 Positive Power Supply. Digital supply.
11
VSS1 Digital ground. 0 Volts
12
F16o Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s.
13
C16o Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
14
C8o Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at
8.192 Mb/s.
15
C4o Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
16
C2o Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at
2.048 Mb/s.
17
F0o Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s.
18
MS1 Mode/Control Select 1 (Input). This input, together with MS2, determines the state
(Normal, Holdover, or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
19
MS2 Mode/Control Select 2 (Input). This input, together with MS1, determines the state
(Normal, Holdover or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
20
F8o Frame Pulse Generic (CMOS Output). This is an 8 kHz 122 ns active high framing pulse,
which marks the beginning of a TDM frame. This is typically used for TDM streams
operating at 8.192 Mb/s.
21 E3DS3/OC3 E3DS3 or OC-3 Selection (Input). In Hardware Mode a low on this pin enables the
differential 155.52 MHz output clock on the C155N/C155P pins; this will also cause the
C34/C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high
on this pin disables the differential 155.52 MHz output clock on the C155N/C155P pins; this
will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no
function if the device is not in Hardware Mode.
3
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