MT8986 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc

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MT8986

CMOS ST-BUS™ FAMILY Multiple Rate Digital Switch

Zarlink Semiconductor Inc 

MT8986

Data Sheet

frame. The interface clock for this operation should be 8.192 MHz. Figure 20 shows the timing for 8.192 Mb/s

operation.

Table 1 summarizes the MT8986 switching configurations for identical I/O data rates.

Serial

Interface

Data Rate

Interface

Clock

required at

CLK Pin

(MHz)

Number of

Input x

Output

Streams

Matrix

Channel

Capacity

Input/Output

Streams Used

Variable/

Constant

throughput

Delay

Selection

2 Mb/s

4.096

8x8

256x256 Non-Blocking

STi0-7/STo0-7

Yes

2 Mb/s

*

4.096

16x8

*

512x256 Blocking

STi0-15/STo0-7

No

2 Mb/s

*

4.096

10x10

128x128 Non-Blocking

STi0-9/STo0-9

Yes

*

(only 4 input x 4-output

can be selected)

Nibble

4.096

8x4

Switching

(2 Mb/s)

512x256 Nibbles

STi0-7/STo0-3

No

4 Mb/s

4.096

8x4

512x256 Blocking

STi0-7/STo0-3

No

4 Mb/s

4.096

4x4

256x256 Non-Blocking

STi0-3/STo0-3

Yes

8 Mb/s

8.192

2x2

256x256 Non-Blocking

STi0-1/STo0-1

Yes

Table 1 - Switching Configurations for Identical Input and Output Data Rates

* - only in the 44 pin packages

Different Input/Output Data Rates

When Different I/O rate is selected by the DMO bit, the input and output data rates should be selected at the IDR

and ODR bits, respectively. The Switching Configuration Bits (SCB) are ignored with this operation. This selection

allows the user to multiplex conventional 2.048 Mb/s serial streams into two higher rates and vice-versa. In addition

to the rate conversion itself, the MT8986 allows for a complete 256 x 256 channel non-blocking switch at different

rates. In this operation, the per-channel variable/constant throughput delay selection is provided.

Depending on which data rates are programmed for input and output streams, the number of data streams used on

the input and output as well as the serial interface clock (CLK input pin) is different. Once the CPU defines the data

rates at the IDR and ODR bits, the MT8986 automatically configures itself with the appropriate number of input and

output streams for the desired operation. Table 2 summarizes the four options available when MT8986 is used with

different I/O rates. Figures 22 to 25 show the timing for each of the four modes shown in Table 2.

Input and Output

Data Rates

2 Mb/s to 4 Mb/s

2 Mb/s to 8 Mb/s

4 Mb/s to 2 Mb/s

8 Mb/s to 2 Mb/s

Interface

Clock

required at

CLK Pin

(MHz)

Number

of Input

x Output

Streams

Matrix

Channel Capacity

Input/Output

Streams Used

4.096

8x4

256x256 Non-Blocking STi0-7/STo0-3

8.192

8x2

256x256 Non-Blocking STi0-7/STo0-1

4.096

8.192

4x8

256x256 Non-Blocking STi0-3/STo0-7

2x8

256x256 Non-Blocking STi0-1/STo0-7

Table 2 - Switching Configurations for Different I/O Data Rates

Variable/

Constant

throughput

Delay Selection

Yes

Yes

Yes

Yes

Input Frame Offset Selection

When 4.096 or 8.192 Mb/s serial interfaces are selected, the MT8986 device provides a feature called Input Frame

Offset allowing the user to compensate for the varying delays at the incoming serial inputs while building large

9

Zarlink Semiconductor Inc.

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