MT8986 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT8986 Datasheet PDF : 46 Pages
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MT8986
Data Sheet
Pin Description
Pin #
40 44 44
DIP PLCC QFP
Name
Description
1
2 40 DTA Data Acknowledgement (Open Drain Output). This active low output indicates
that a data bus transfer is complete. A 10 kΩ pull-up resistor is required at this
output.
2-7 3-5 41-43 STi0-5 ST-BUS Inputs 0 to 5 (Inputs). Serial data input streams. These streams may
7-9 1-3
have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels,
respectively.
8 10 4 STi6/A6 ST-BUS Input 6/Addr.6 input (Input). The function of this pin is determined by
the switching configuration enabled. If non-multiplexed CPU bus is used along
with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address
input function. For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed
CPU bus (44 pin only) is selected, this pin assumes STi6 function. See Control
Register bits description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A6 and STi6 inputs are required
simultaneously (e.g., 8 x 4 switching configuration at 4.096 Mb/s or rate
conversion between 2.048 Mb/s to 4.196 or 8.192 Mb/s) the A6 input should be
connected to pin STo6/A6.
9 11 5 STi7/A7 ST-BUS Input 7/Addr.7 input (Input): The function of this pin is determined by
the switching configuration enabled. If non-multiplexed CPU bus is used along
with a higher input rate of 8.192 Mb/s, this pin provides A7 address input
function.
For 2.048 and 4.096 Mb/s (8x4) applications or when multiplexed CPU bus
(44 pin only) is selected, this pin assumes STi7 function. See Control Register
bits description and Tables 1, 2, 6 & 7 for more details.
Note that for applications where both A7 and STi7 inputs are required
simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should
be connected to pin STo7/A7.
10 12 6
11 13 7
VDD +5 Volt Power Supply.
FR Frame Pulse (Input). This input accepts and automatically identifies frame
synchronization signals formatted according to ST-BUS and GCI interface
specifications.
12 14
8
CLK Clock (Input). Serial clock for shifting data in/out on the serial streams.
Depending on the serial interface speed selected by IMS (Interface Mode Select)
register, the clock at this pin can be 4.096 or 8.192 MHz.
13-15 15-17 9-11 A0-2/ Address 0-2 / Input Streams 8-10 (Input). When non-multiplexed CPU bus is
STi8-10 selected, these lines provide the A0-A2 address lines to MT8986 internal
registers. When 16x8 switching configuration is selected (in 44 pin only), then
these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s.
16-18
19-21
13-15
A3-5/ Address 3-5 / Input Streams 11-13 (Input). When non-multiplexed CPU bus is
STi11-13 selected, these lines provide the A3-A5 address lines to MT8986 internal
registers. When 16x8 switching configuration is selected (in 44 pin only), then
these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s.
3
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