MT9079 Просмотр технического описания (PDF) - Mitel Networks

Номер в каталоге

Компоненты Описание

производитель

MT9079

CMOS ST-BUS™ FAMILY Advanced Controller for E1

Mitel Networks 

MT9079

8) When CRC-4 multiframing has been achieved,

the primary basic frame alignment and resulting

multiframe alignment will be adjusted to the basic

frame alignment determined during CRC-4

synchronization. Therefore, the primary basic frame

alignment will not be updated during the CRC-4

multiframing search, but will be updated when the

CRC-4 multiframing search is complete.

Channel Signalling

When control bit TxCAS is low the MT9079 is in

Channel Associated Signalling mode (CAS); when

TxCAS is high it is in Common Channel Signalling

(CCS) mode. The CAS mode ABCD signalling

nibbles can be passed either via the micro-ports

(RPSIG = 1) or through related channels of the

CSTo1 and CSTi2 serial links (RPSIG = 0), see

Figure 4. Memory page five contains the receive

ABCD nibbles and page six the transmit ABCD

nibbles for micro-port CAS access.

In CAS operation an ABCD signalling bit debounce

of 14 msec. can be selected (DBNCE = 1). This is

consistent with the signalling recognition time of

CCITT Q.422. It should be noted that there may be

as much as 2 msec. added to this duration because

signalling equipment state changes are not

synchronous with the PCM 30 multiframe.

If basic frame synchronization is lost (page 3,

address 10H, SYNC = 1) all receive CAS signalling

nibbles are frozen. Receive CAS nibbles will become

unfrozen when basic frame synchronization is

acquired.

When the SIGI interrupt is unmasked, IRQ will

become active when a signalling nibble state change

is detected in any of the 30 receive channels. The

SIGI interrupt mask is located on page 1, address

1CH, bit 0; and the SIGI interrupt vector (page 4,

address 12H) is 01H.

Loopbacks

In order to meet PRI Layer 1 requirements and to

assist in circuit fault sectionalization the MT9079 has

six loopback functions. These are as follows:

a) Digital loopback (DSTi to DSTo at the PCM 30

side). Bit DLBK = 0 normal; DLBK = 1 activate.

DSTi

System

DSTo

MT9079

Tx

PCM30

b) Remote loopback (RxA and RxB to TxA and TxB

respectively at the PCM 30 side). Bit RLBK = 0

normal; RLBK = 1 activate.

System

DSTo

MT9079

Tx

PCM30

Rx

c) ST-BUS loopback (DSTi to DSTo at the system

side). Bit SLBK = 0 normal; SLBK = 1 activate.

DSTi

System

DSTo

MT9079

Tx

PCM30

d) Payload loopback (RxA and RxB to TxA and TxB

respectively at the system side with FAS and NFAS

operating normally). Bit PLBK = 0 normal; PLBK = 1

activate. The payload loopback is effectively a

physical connection of DSTo to DSTi within the

MT9079. Channel zero and the DL originate at the

point of loopback.

DSTi

System

DSTo

MT9079

Tx

Rx PCM30

e) Local and remote time slot loopback. Remote

time slot loopback control bit RTSL = 0 normal; RTSL

= 1 activate, will loop around transmit ST-BUS time

slots to the DSTo stream. Local time slot loopback

bits LTSL = 0 normal; LTSL = 1 activate, will loop

around receive PCM 30 time slots towards the

remote PCM 30 end.

DSTi

System

DSTo

MT9079

Tx

PCM30

Rx

The digital, remote, ST-BUS and payload loopbacks

are located on page 1, address 15H, control bits 3 to

0. The remote and local time slot loopbacks are

controlled through control bits 4 and 5 of the per time

slot control words, pages 7 and 8.

4-251

Share Link: