MT9076AB Просмотр технического описания (PDF) - Mitel Networks

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MT9076AB

T1/E1/J1 3.3V Single Chip Transceiver

Mitel Networks 

Preliminary Information

MT9076

Data Link

T1/J1 Mode

• Three methods are provided to access the

datalink:

1. TxDL and RxDL pins support transmit and

receive datalinks

2. Bit Oriented Messages are supported via

internal registers

3. An internal HDLC can be assigned to transmit/

receive over the FDL in ESF mode

E1 Mode

• Two methods are provided to access the

datalink:

1. TxDL and RxDL pins support transmit and

receive datalinks over the Sa4~Sa8 bits

2. An internal HDLC can be assigned to transmit/

receive data via the Sa4~Sa8 bits

• In transparent mode, if the Sa4 bit is used for

an intermediate datalink, the CRC-4

remainder can be updated to reflect changes

to the Sa4 bit

Access and Monitoring for National (Sa) Bits (E1 mode only)

• In addition to the datalink functions, the Sa bits can be accessed using:

• Single byte register

• Five byte transmit and receive national bit buffers

• A maskable interrupt is generated on the change of state of any Sa bit

Three Embedded Floating HDLCs (HDLC0, HDLC1, HDLC2)

• Successive writes/reads can be made to the transmit/receive FIFOs at 160 ns or 80ns intervals

• Flag generation and Frame Check Sequence (FCS) generation and detection, zero insertion and

deletion

• Continuous flags, or continuous 1s are transmitted between frames

• Transmit frame-abort

• Transmit end-of-packet after a programmable number of bytes (up to 65,536 bytes)

• Invalid frame handling:

• Frames yielding an incorrect FCS are tagged as bad packets

• Frames with fewer than 25 bits are ignored

• Frames with fewer than 32 bits between flags are tagged as bad packets

• Frames interrupted by a Frame-Abort sequence remain in the FIFO and an interrupt is generated

• Access is provided to the receive FCS

• FCS generation can be inhibited for terminal adaptation

• Recognizes single byte, dual byte and all call addresses

• Independent, 16-128 byte deep transmit and receive FIFOs

• Receive FIFO maskable interrupts for near full (programmable levels) and overflow conditions

• Transmit FIFO maskable interrupts for nearly empty (programmable levels) and underflow conditions

• Maskable interrupts for transmit end-of-packet and receive end-of-packet

• Maskable interrupts for receive bad-frame (includes frame abort)

• Transmit-to-receive and receive-to-transmit loopbacks are provided

• Transmit and receive bit rates and enables are independent

• Frame aborts can be sent under software control and they are automatically transmitted in the event of

a transmit FIFO underrun

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