MT9075A Просмотр технического описания (PDF) - Mitel Networks

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MT9075A

E1 Single Chip Transceiver

Mitel Networks 

MT9075A

Preliminary Information

• A short frame exists if there are less than 25

bits between the flags. Short frames are

ignored by the receiver and nothing is written

to the receive FIFO.

• Packets which are at least 25 bits in length

but less than 32 bits between the flags are

also invalid. In this case the data is written to

the FIFO but the last byte is tagged with a

“bad packet” indication.

• If a frame abort sequence is detected the

packet is invalid. Some or all of the current

packet will reside in the receive FIFO,

assuming the packet length before the abort

sequence was at least 26 bits long.

Frame Abort

The transmitter will abort a current packet by

substituting a zero followed by seven contiguous 1s

in place of the normal packet. The receiver will abort

upon reception of seven contiguous 1s occurring

between the flags of a packet which contains at least

26 bits.

Note that should the last received byte before the

frame abort end with contiguous 1s, these are

included in the seven 1s required for a receiver

abort. This means that the location of the abort

sequence in the receiver may occur before the

location of the abort sequence in the originally

transmitted packet. If this happens then the last data

written to the receive FIFO will not correspond

exactly with the last byte sent before the frame abort.

Interframe Time Fill and Link Channel States

When the HDLC transmitter is not sending packets it

will wait in one of two states

• Interframe Time Fill state: This is a

continuous series of flags occurring between

frames indicating that the channel is active

but that no data is being sent.

• Idle state: An idle Channel occurs when at

least 15 contiguous 1s are transmitted or

received.

In both states the transmitter will exit the wait state

when data is loaded into the transmitter FIFO.

Go-Ahead

A go-ahead is defined by a 9 bit sequence

"011111110" (contiguous 7Fs) and hence is the

occurrence of a frame abort sequence followed by a

zero. This feature is used to distinguish a proper in-

packet frame abort sequence from one occurring

outside of a packet for some special applications

HDLC Functional Description

The HDLC controller can be reset by either the reset

pin (RESET, pin 11 in PLCC or pin 84 in MQFP) or by

the control bit HRST at address 1BH in page 0BH

(for HDLC0) or page 0CH (for HDLC1). When reset,

the HDLC Control Registers are cleared, resulting in

the transmitter and receiver being disabled. The

receiver and transmitter can be enabled independent

of each other through Control Register 1 at address

13H. The transceiver input and output are enabled

when the enable control bits in Control Register 1

are set. Transmit to receive loopback as well as a

receive to transmit loopback are also supported.

Transmit and receive bit rates and enables can

operate independently.

Received packets from the serial interface are

sectioned into bytes by an HDLC receiver that

detects flags, checks for go-ahead signals, removes

inserted zeros, performs a cyclical redundancy

check (CRC) on incoming data, and monitors the

address if required. Packet reception begins upon

detection of an opening flag. The resulting bytes are

concatenated with two status bits (RQ9 and RQ8 at

address 14H) and placed in a receiver first-in-first-

out buffer (RX FIFO). Register 14H also contains

control bits that generate status and interrupts for

microprocessor read control.

In conjunction with the control circuitry, the

microprocessor writes data bytes into a transmit

buffer (TX FIFO) register that generates status and

interrupts. Packet transmission begins when the

microprocessor writes a byte to the TX FIFO. Two

status bits are added to the TX FIFO for transmitter

control of frame aborts (FA) and end of packet (EOP)

flags. Packets have flags appended, zeros inserted,

and an FCS, added automatically during serial

transmission. When the TX FIFO is empty and

finished sending a packet, Interframe Time Fill bytes

(continuous flags (7E hex)), or Mark Idle (continuous

ones) are transmitted to indicate that the channel is

idle.

HDLC Transmitter

Following initialization and enabling, the transmitter

is in the Idle Channel state (Mark Idle), continuously

sending ones. Interframe Time Fill state (Flag Idle) is

selected by setting the Mark Idle bit in Control

Register 1 to one. The transmitter remains in either

of these two states until data is written to the TX

FIFO. Control Register 1 bits EOP (End Of Packet)

and FA (Frame Abort) are set as status bits before

the microprocessor loads 8 bits of data into the 10 bit

wide FIFO (8 bits data and 2 bits status). To change

4-146

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