MT9075A Просмотр технического описания (PDF) - Mitel Networks

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MT9075A

E1 Single Chip Transceiver

Mitel Networks 

Preliminary Information

MT9075A

Two status bits, RSLIP and RSLPD (page 03H,

address 15H), give indication of a slip occurrence

and direction. RSLIP changes state in the event of a

slip. If RSLPD=0, the slip buffer has overflowed and a

frame was lost; if RSLPD=1, a underflow condition

occurred and a frame was repeated. A maskable

interrupt SLPI (page 01H, address 1BH) is also

provided.

Figure 9 illustrates the relationship between the read

and write pointers of the receive slip buffer.

Measuring clockwise from the write pointer, if the

read pointer comes within two channels of the write

pointer a frame slip will occur, which will put the read

pointer 34 channels from the write pointer.

Conversely, if the read pointer moves more than 60

channels from the write pointer, a slip will occur,

which will put the read pointer 28 channels from the

write pointer. This provides a worst case hysteresis

of 13 channels peak (26 channels peak-to-peak) or a

wander tolerance of 208 UI.

Framing Algorithm

The MT9075A contains three distinct framing

algorithms: basic frame alignment, signalling

multiframe alignment and CRC-4 multiframe

alignment. Figure 10 is a state diagram that

illustrates these algorithms and how they interact.

After power-up, the basic frame alignment framer will

search for a frame alignment signal (FAS) in the PCM

30 receive bit stream. Once the FAS is detected, the

corresponding bit 2 of the non-frame alignment

signal (NFAS) is checked. If bit 2 of the NFAS is zero

a new search for basic frame alignment is initiated. If

bit 2 of the NFAS is one and the next FAS is correct,

the algorithm declares that basic frame

synchronization has been found (i.e., page 03H,

address 10H, bit 7, SYNC is zero).

Once basic frame alignment is acquired the

signalling and CRC-4 multiframe searches will be

initiated. The signalling multiframe algorithm will

align to the first multiframe alignment signal pattern

(MFAS = 0000) it receives in the most significant

nibble of channel 16 (page 3, address 10H, bit 6,

MFSYNC = 0). Signalling multiframing will be lost

when two consecutive multiframes are received in

error.

The CRC-4 multiframe alignment signal is a 001011

bit sequence that appears in PCM 30 bit position one

of the NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table

7). In order to achieve CRC-4 synchronization two

CRC-4 multiframe alignment signals must be

received without error (page 03H, address 10H, bit 5,

CRCSYN = 0) within 8 msec.

The MT9075A framing algorithm supports automatic

interworking of interfaces with and without CRC-4

processing capabilities. That is, if an interface with

CRC-4 capability, achieves valid basic frame

alignment, but does not achieve CRC-4 multiframe

alignment by the end of a predefined period, the

distant end is considered to be a non-CRC-4

interface. When the distant end is a non-CRC-4

interface, the near end automatically suspends

receive CRC-4 functions, continues to transmit CRC-

4 data to the distant end with its E-bits set to zero,

and provides a status indication. Naturally, if the

distant end initially achieves CRC-4 synchronization,

CRC-4 processing will be carried out by both ends.

This feature is selected when control bit AUTC (page

01H, address 11H) is set to zero.

Read Pointer Write Pointer Read Pointer

60 CH

2 CH

47 CH

512 Bit

Elastic

Store

15 CH

13 CH

Wander Tolerance

34 CH

Read Pointer

28 CH

Read Pointer

-13 CH

Figure 9 - Read and Write Pointers in the Slip Buffers

4-149

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