MT9075A Просмотр технического описания (PDF) - Mitel Networks
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MT9075A Datasheet PDF : 78 Pages
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MT9075A
Preliminary Information
MT9075A
OSC1
1MΩ
OSC2
20MHz
56pF 39pF
100Ω
1µH*
Note: the 1µH inductor is optional
Figure 7 - Crystal Oscillator Circuit
Jitter Attenuator (JA)
The MT9075A Jitter Attenuator (JA), which consists
of a Phase Locked Loop (PLL) and data FIFO, can
be used on either the transmit or receive side of the
interface.
On the transmit side the C4b signal clocks the data
into the FIFO, the PLL de-jitters the C4b clock and
the resulting clean C4b signal clocks the data out of
the FIFO.
When the JA is selected on the receive side, the
extracted clock signal clocks the data into the FIFO.
The same clock feeds the PLL and the resulting de-
jittered clock is used to clock the data out of the
FIFO.
The JA meets the jitter transfer characteristics as
proposed by G.823 and the relevant
recommendations as shown in Figure 8. The JA
FIFO depth can be selected to be from 16 to 128
words deep, in multiples of 16 (2-bit) words. Its read
pointer can be centered by changing the JFC bit
(address 18H of page 02H) to provide maximum jitter
tolerance. If the read pointer should come within 4
bits of either end of the FIFO, the read clock
frequency will be increased or decreased by 0.0625
UI to correct the situation. The maximum time
needed to centre is Tmax= 3904∗Depth ns, where
Depth is the selected JA FIFO depth. During this
time the JA will not attenuate jitter.
To ensure normal operation, the JA FIFO depth
should be set in software to be larger than the
anticipated maximum UI of input jitter.
Clock Jitter Attenuation Modes
MT9075A has three basic jitter attenuation modes of
operation, selected by the BS/LS and BL/FR control
pins.
• System Bus Synchronous Mode.
• Line Synchronous Mode.
• Free-run mode.
dB
0.5
0
-20 dB/decade
-19.5
10
40
400
10K
Frequency (Hz)
Figure 8 - Typical Jitter Attenuation Curve
4-138
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