MT4LC16M4G3 Просмотр технического описания (PDF) - Micron Technology
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MT4LC16M4G3 Datasheet PDF : 22 Pages
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DRAM REFRESH (Continued)
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller uses RAS#-ONLY or burst CBR refresh, all rows
RAS#
V IH
V IL
16 MEG x 4
EDO DRAM
must be refreshed with a refresh rate of tRC minimum
prior to resuming normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
CAS#
V IH
V IL
ADDR
V IH
V IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ VVIIOOHL
OE#
V
V
IH
IL
RAS#
V IH
V IL
CAS#
V
V
IH
IL
ADDR
V IH
V IL
OPEN
VALID DATA (A)
tOD
tOES
tOE
VALID DATA (A)
VALID DATA (B)
tOD
tOEHC
VALID DATA (C)
tOD
tOEP
VALID DATA (D)
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
Figure 1
OE# Control of DQs
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ
V IOH
V IOL
WE# VVIIHL
OE# VVIIHL
OPEN
VALID DATA (A)
tWHZ
tWPZ
VALID DATA (B)
tWHZ
INPUT DATA (C)
The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2
WE# Control of DQs
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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