1Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 103: REFRESH to Power-Down Entry .................................................................................................. 188
Figure 104: ACTIVATE to Power-Down Entry ................................................................................................. 189
Figure 105: PRECHARGE to Power-Down Entry ............................................................................................. 189
Figure 106: MRS Command to Power-Down Entry ......................................................................................... 190
Figure 107: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 190
Figure 108: RESET Sequence ......................................................................................................................... 192
Figure 109: On-Die Termination ................................................................................................................... 193
Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 198
Figure 111: Dynamic ODT: Without WRITE Command .................................................................................. 198
Figure 112: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 199
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 200
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 200
Figure 115: Synchronous ODT ...................................................................................................................... 202
Figure 116: Synchronous ODT (BC4) ............................................................................................................. 203
Figure 117: ODT During READs .................................................................................................................... 205
Figure 118: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 207
Figure 119: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry ............ 209
Figure 120: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 211
Figure 121: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 213
Figure 122: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 213
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.