128M16 Просмотр технического описания (PDF) - Micron Technology

Номер в каталоге

Компоненты Описание

производитель

128M16

DDR3 SDRAM

Micron Technology 

2Gb: x4, x8, x16 DDR3 SDRAM

Features

Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 186

Figure 104: MRS Command to Power-Down Entry ......................................................................................... 187

Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 187

Figure 106: RESET Sequence ......................................................................................................................... 189

Figure 107: On-Die Termination ................................................................................................................... 190

Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 195

Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 195

Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 196

Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 197

Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 197

Figure 113: Synchronous ODT ...................................................................................................................... 199

Figure 114: Synchronous ODT (BC4) ............................................................................................................. 200

Figure 115: ODT During READs .................................................................................................................... 202

Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 204

Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off ) Entry ............ 206

Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off ) Exit ............... 208

Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 210

Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 210

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

8

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‹ 2006 Micron Technology, Inc. All rights reserved.

Share Link: