MT41J128M16 Просмотр технического описания (PDF) - Micron Technology

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производитель

MT41J128M16

DDR3 SDRAM

Micron Technology 

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 512 Meg x 4 Functional Block Diagram

ODT

ZQ

RZQ RESET#

CKE

VSSQ A12

CK, CK#

CS#

RAS#

CAS#

WE#

Control

logic

Mode registers

18

A[14:0]

BA[2:0]

18 Address

register

ZQCL, ZQCS

ZQ CAL

To pullup/pulldown

networks

ODT

control

BC4 (burst chop)

OTF

Refresh

counter

15

Row-

15

address

MUX

15

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

Bank 7

Bank 6

Bank 5

Bank 4

Bank 3

Bank 2

Bank 1

Bank 0

row-

address

latch

and

decoder

32,768

Bank 0

memory

array

(32,768 x 256 x 32)

Sense amplifiers

8,192

3

Bank

control

logic

3

I/O gating

DM mask logic

256

(x32)

Column

decoder

Column-

8

11

address

counter/

latch

3

Columns 0, 1, and 2

Columns 0, 1, and 2

READ

32

FIFO

4

and

data

MUX

CK,CK#

DLL

READ

drivers

32

BC4

BC4

OTF

DM

WRITE

32

Data

4

drivers

interface

Data

and

input

logic

CK,CK#

Column 2

(select upper or

lower nibble for BC4)

VDDQ/2

RTT,nom RTT(WR)

SW1

SW2

DQ[3:0]

DQS, DQS#

(1 . . . 4)

DQ[3:0]

VDDQ/2

RTT,nom RTT(WR)

SW1

SW2

(1, 2)

VDDQ/2

RTT,nom RTT(WR)

SW1

SW2

DQS, DQS#

DM

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

14

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