2Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Features
• VDD = VDDQ = 1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• Posted CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL) based on
tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
• Self refresh temperature (SRT)
• Write leveling
• Multipurpose register
• Output driver calibration
Options1
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. M, K
– 78-ball (9mm x 11.5mm) Rev. D
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) Rev. D
– 96-ball (8mm x 14mm) Rev. K
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C)
– Industrial (–40°C ≤ TC ≤ +95°C)
• Revision
Marking
512M4
256M8
128M16
DA
HX
HA
JT
-093
-107
-125
-15E
-187E
None
IT
:D/:M/:K
Note:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-0931, 2, 3, 4
-1071, 2, 3
-1251, 2,
-15E1,
-187E
Data Rate (MT/s)
2133
1866
1600
1333
1066
Target tRCD-tRP-CL
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
Notes:
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
4. Backward compatible to 1866, CL = 13 (-107).
tRCD (ns)
13.09
13.91
13.75
13.5
13.1
tRP (ns)
13.09
13.91
13.75
13.5
13.1
CL (ns)
13.09
13.91
13.75
13.5
13.1
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.