MT28F322P3 Просмотр технического описания (PDF) - Micron Technology

Номер в каталоге

Компоненты Описание

производитель

MT28F322P3

FLASH MEMORY

Micron Technology 

PRELIMINARY

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

Table 5

Command Descriptions (continued)

CODE DEVICE MODE

D0h Erase Confirm

Program/Erase

Resume

D0h FPA Confirm

FFh Read Array

01h Lock Block

2Fh Lock Down

D0h Unlock Block

00h Invalid /Reserved

BUS CYCLE

DESCRIPTION

Second

If the previous command was an ERASE SETUP command, then the

CSM will close the address and data latches, and it will begin erasing

the block indicated on the address balls. During programming/erase,

the device will respond only to the READ STATUS REGISTER,

PROGRAM SUSPEND, or ERASE SUSPEND commands and will output

status register data on the falling edge of OE# or CE#, whichever

occurs last.

First

If a PROGRAM or ERASE operation was previously suspended, this

command will resume the operation.

Second If the previous command was FPA SETUP, the CSM will latch the

address indicated on the address bus and enter the FPA mode.

First

During the array mode, array data will be output on the data bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock the block indicated on the

address bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock down the block indicated on

the address bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and unlock the block indicated on the

address bus. If the block had been previously set to lock down, this

operation will have no effect.

Unassigned command that should not be used.

logic HIGH level and the CSM responds to the full com-

mand set. The CSM stays in the current command state

until the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when VPP is within its correct volt-

age range.

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the VPP status bit (SR3), the pro-

gram status bit (SR4), and the erase status bit (SR5) of

the status register. The CLEAR STATUS REGISTER com-

mand (50h) allows the external microprocessor to clear

these status bits and synchronize to the internal op-

erations. When the status bits are cleared, the device

returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REG-

ISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code

FFh on DQ0–DQ7. Control signals CE# and OE# must

be at a logic LOW level (VIL), and WE# and RST# must be

at logic HIGH level (VIH) to read data from the array.

Data is available on DQ0–DQ15. Any valid address

within any of the blocks selects that address and allows

data to be read from that address. Upon initial power-

up or device reset, the device defaults to the read array

mode.

READ PROTECTION CONFIGURATION DATA

The chip identification mode outputs three types

of information: the manufacturer/device identifier, the

block locking status, and the protection register. Two

bus cycles are required for this operation: the chip iden-

tification data is read by entering the command code

90h on DQ0–DQ7 to the bank containing address 0h

and the identification code address on the address

lines. Control signals CE# and OE# must be at a logic

LOW level (VIL), and WE# and RST# must be at a logic

HIGH level (VIH) to read data from the protection con-

2 Meg x 16 Async/Page Flash Memory

MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

Share Link: