M48T18-100PC Просмотр технического описания (PDF) - STMicroelectronics

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M48T18-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

M48T08, M48T18

Table 7. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)

Symbol

Parameter

Min

Max

Unit

tPD

E1 or W at VIH or E2 at VIL before Power Down

0

µs

tF (1)

VPFD (max) to VPFD (min) VCC Fall Time

300

µs

tFB (2)

VPFD (min) to VSO VCC Fall Time

10

µs

tR

VPFD(min) to VPFD (max) VCC Rise Time

0

µs

tRB

VSO to VPFD (min) VCC Rise Time

1

µs

tREC

E1 or W at VIH or E2 at VIL after Power Up

1

ms

tPFX

tPFH(3)

INT Low to Auto Deselect

VPFD (max) to INT High

10

40

µs

120

µs

Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after

VCC passes VPFD (min).

2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.

3. INT may go high anytime after VCC exceeds VPFD (min) and is guaranteed to go high tPFH after VCC exceeds VPFD (max).

Figure 5. Power Down/Up Mode AC Waveforms

VCC

VPFD (max)

VPFD (min)

VSO

tF

tPD

INT

tFB

tPFX

INPUTS

RECOGNIZED

OUTPUTS

VALID

(PER CONTROL INPUT)

tDR

tRB

DON’T CARE

HIGH-Z

tR

tPFH

NOTE

tREC

RECOGNIZED

VALID

(PER CONTROL INPUT)

AI00566

Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1high or E2 low as VCC rises past VPFD(min).

Some systems may performs inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begins. Even

though a power on reset is being applied to the processor a reset condition may not occur until after the system clock is running.

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