M48T18-100PC Просмотр технического описания (PDF) - STMicroelectronics

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M48T18-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

M48T08, M48T18

– SL1 = 41 yrs, SL2 = 11.4 yrs

– TT = 8760 hrs/yr

– TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr

Predicted storage life ≥

1

{[(8322/8760)/41]+[(431/8760)/11.4]}

or 36 years.

Cell Capacity Life

The M48T08,18 internal cell has a rated capacity

of 50mAh. The device places a nominal RAM and

TIMEKEEPER load of less than 520nA at room

temperature. At this rate, the capacity consumption

life is 50E-3/520E-9 = 96,153 hours or about 11

years. Capacity consumption life can be extended

by applying VCC or turning off the clock oscillator

prior to system power down.

Calculating Capacity Life

The RAM and TIMEKEEPER load remains rela-

tively constant over the operating temperature

range. Thus, worst case cell capacity life is essen-

tially a function of one variable, VCC duty cycle. For

example, if the oscillator runs 100% of the time with

VCC applied 60% of the time, the capacity con-

sumption life is 10/(1-0.6), or 25 years.

Estimated System Life

Since either storage life or capacity consumption

can end the battery’s life, the system life is marked

by which ever occurs first. In the above example,

this would be 25 years.

Reference for System Life

Each M48T08,18 is marked with a nine digit manu-

facturing date code in the form of H99XXYYZZ. For

example, H995B9431 is:

H = fabricated in Carrollton, TX

9 = assembled in Muar, Malaysia,

9 = tested in Muar, Malaysia,

5B = lot designator,

9431 = assembled in the year 1994, work week 31.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data

registers, and not the actual clock counters, updat-

ing the registers can be halted without disturbing

the clock itself.

Updating is halted when a ’1’ is written to the READ

bit, the seventh bit in the control register. As long as

a ’1’ remains in that position, updating is halted.

After a halt is issued, the registers reflect the count;

that is, the day, date, and the time that were current

at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating is within a second after the bit

is reset to a ’0’.

Setting the Clock

The eighth bit of the control register is the WRITE

bit. Setting the WRITE bit to a ’1’, like the READ bit,

halts updates to the TIMEKEEPER registers. The

user can then load them with the correct day, date,

and time data in 24 hour BCD format (see Table

10). Resetting the WRITE bit to a ’0’ then transfers

the values of all time registers (1FF9h-1FFFh) to

the actual TIMEKEEPER counters and allows nor-

mal operation to resume. The FT bit and the bits

marked as ’0’ in Table 10 must be written to ’0’ to

allow for normal TIMEKEEPER and RAM opera-

tion.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP bit

is the MSB of the seconds register. Settingit to a ’1’

stops the oscillator. The M48T08,18is shippedfrom

SGS-THOMSON with the STOP bit set to a ’1’.

When reset to a ’0’, the M48T08,18 oscillator starts

within 1 second.

Calibrating the Clock

The M48T08,18 is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz. A

typical M48T08,18 is accurate within ±1 minute per

month at 25°C without calibration. The devices are

tested not to exceed 35 PPM (parts per million)

oscillator frequency error at 25°C, which equates to

about ± 1.53 minutes per month. Of course the

oscillation rate of any crystal changes with tem-

perature. Figure 11 shows the frequency error that

can be expected at various temperatures. Most

clock chips compensate for crystal frequency and

temperature shift error with cumbersome trim ca-

pacitors. The M48T08,18 design, however, em-

ploys periodic counter correction. The calibration

circuit adds or subtracts counts from the oscillator

divider circuit at the divide by 128 stage, as shown

in Figure 10. The number of times pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five bit Calibration byte found

in the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order

bits in the Control register. This byte can be set to

represent any value between 0 and 31 in binary

11/18

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