MSM9225GS-2K Просмотр технического описания (PDF) - Oki Electric Industry

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MSM9225GS-2K

CAN (Controller Area Network) Controller

Oki Electric Industry 

¡ Semiconductor

MSM9225

(3) Bit timing

Bit timing is set by CAN bus timing registers 0 and 1. The relationship between 1 bit time

of a message and a CAN bus timing (the MSM9225 register) is as follows:

1 bit time

SYNC-SEG PROP-SEG

PHASE-SEG1

PHASE-SEG2

SJW1

TSEG1

TSEG2

SJW2

(BTR0 : SJWB/A) (BTR1 : TSEG13-10) (BTR1 : TSEG22-20) (= SJW1)

1BTL

cycle

Sampling

point

If setting is :

BTR0 = "01000001" ...SJWB = "0" SJWA = "1" BRP5-0 = "000001"

BTR1 = "00000001"...TSEG2 = "000" TSEG1 = "0001"

then the bit timing is as follows

Sync segment

SJW 1

TSEG 1

TSEG 2

SJW 2

1 bit time

1 BTL cycle (fixed)

2 BTL cycle

2 BTL cycle

1 BTL cycle

2 BTL cycle

8 BTL cycle

Sampling point = 5 BTL cycle

If fosc = 16 MHz, then 1 BTL cycle is :

BTL cycle = 2 ¥ (25 ¥ 0 + 24 ¥ 0 + 23 ¥ 0 + 22 ¥ 0 + 21 ¥ 0 + 1 + 1) / 16 MHz = 0.25 ms

Therefore 1 bit time is :

8 BTL cycle = 8 ¥ 0.25 ms = 2.0 ms

(= 500 Kb/s)

6. Communication input/output control register (TIOC: 2Fhex)

This register sets the communication mode and output buffer format.

Writing to the TIOC bit is enabled, when the INIT bit of the CAN control register (CANC:

0Ehex) is "1".

The bit configuration is as follows:

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