MSM80C39 Просмотр технического описания (PDF) - Oki Electric Industry
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MSM80C39 Datasheet PDF : 20 Pages
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¡ Semiconductor
MSM80C48/49/50, MSM80C35/39/40
PIN DESCRIPTIONS
Symbol
P10-P17
(PORT 1)
P20-P27
(PORT 2)
Type
I/O
I/O
DB0-DB7
I/O
(BUS)
T0
I/O
(Test 0)
Description
8-bit quasi-bidirectional port
8-bit quasi-bidirectional port
The high-order four bits of external program memory addresses can be output
from P2.0-P2.3, to which the I/O expander MSM82C43RS may also be connected.
Bidirectional port
The low-order eight bits of external program memory address can be output
from this port, and the addressed instruction is fetched under the control of
PSEN signal. Also, the external data memory address is output, and data is
read and written synchronously using RD and WR signals.
The port can also serve as either a statically latched output port or a
non-latching input port.
The input can be tested with the conditional jump instructions JT0 and JNT0.
The execution of the ENT0 CLK instruction causes a clock output.
T1
(Test 1)
I
The input can be tested with the conditional jump instructions JT1 and JNT1.
The execution of a STRT CNT instruction causes an internal counter input.
INT
(Interrupt)
I
Interrupt input. If interrupt is enabled, INT input initiates an interrupt.
Interrupt is disabled after a reset.
Also testable with a JNI instruction. Can be used to terminate the power-down
mode. (Active "0" level)
RD
(Read)
WR
(Write)
ALE
Address &
Data Latch
Clock
O
A signal to read data from external data memory. (Active "0" level)
O
A signal to write data to external data memory. (Active "0" level)
O
This signal is generated in each cycle. It may be used as a clock output.
External data memory or external program memory is addressed upon the
falling edge. For the external ROM, this signal is used to latch the bus port data
upon the ALE signal rise-up after the execution of the OUTL BUS, A instruction.
PSEN Program
Store Enable
RESET
SS
(Single Step)
O
A signal to fetch an instruction from external program memory
(Active "0" level)
I
RESET input initialize the processor. (Active "0" level)
Used to terminate the power-down mode.
I
A program is executed step by step. This pin can also be used to control
internal oscillation when the power-down mode is reset.
(Active "0" level)
EA
I
When held at high level, all instructions are fetched from external memory.
(External Access)
(Active "1" level)
PROG
O
This output strobes the MSM82C43RS I/O expander.
(Expander Strobe)
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