MSM6789L Просмотр технического описания (PDF) - Oki Electric Industry

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Компоненты Описание

производитель

MSM6789L

SBC Solid-State Recorder IC

Oki Electric Industry 

MSM6789A/6789L

¡ Semiconductor

PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)

Pin Symbol Type

Description

Bit Rate Selection. This pin selects one of the following three types of bit rate (master

clock frequency fOSC = 8.192 MHz). This pin is invalid during the ROM playback operation.

35 BRO

I

36 BR1

BR1

BR0

L

L

L

H

H

L

H

H

Bit rate

16.0 kbps

12.6 kbps

10.0 kbps

Unused

Transition to the Power-down State.

Low level: The MSM6789A automatically goes to the power-down state, except

when the record/playback operation is performed.

High level: The MSM6789A automatically goes to the standby state, instead of the

33 PDMD*1

I

power-down state, except when the record/playback operation

is performed. In this case, the MSM6789A can be placed in the

power-down state by setting the RESET or PDWN pin to a high level.

If an external circuit is used for the built-in LPF, this standby mode

must be selected by applying a high level to the PDMD pin.

These pins set the voice detect level for the voice triggered starting and unvoiced-part

67-70 VD0-VD3 I

elimination.

This pin selects the voice triggered starting or the unvoiced-part elimination.

Voice triggered starting: Input a High level to the VDS pin. Then set the voice

detect level with VD0 to VD3 pins.

38 VDS

I

Unvoiced-part elimination:Input a Low level to the VDS pin. Then set the voice

detect level with VD0 to VD3 pins.

Note: When neither the voice triggered starting nor the unvoiced-part elimination is

used, input a Low level to VD0 to VD3.

72 MON

O This pin outputs a high level while the record/playback operation is being performed.

Output to indicate the enable or disable state of the operation for specifying a

71 NAR

O phrase. When continuous ROM playback is performed, the next phrase can

be specified after the NAR pin goes to high positively.

*1 When DRAM is selected, be sure to set the PDMD pin to a High level.

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