MSM5299C Просмотр технического описания (PDF) - Oki Electric Industry
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MSM5299C Datasheet PDF : 11 Pages
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¡ Semiconductor
MSM5299C
FUNCTIONAL DESCRIPTION
Pin Functional Description
• ER, EL
Pin
Input/Output
SHL
Description
ER
Input
EL
Output
Input pin to ENABLE F/F of MSM5299C.
L
Output pin of ENABLE F/F. EL is connected to next MSM5299C's
ER when MSM5299Cs are connected in series (cascade
connection).
EL
Input
ER
Output
Input pin to ENABLE F/F of MSM5299C.
Output pin of ENABLE F/F. ER is connected to next MSM5299C's
H EL when MSM5299Cs are connected in series (cascade
connection).
When a single MSM5299C device is used, ER (EL) should be set at "L" level.
When a cascade connection is required, set the first MSM5299C's ER (EL) pin at "L" level and
connect the next MSM5299C's EL (ER) pin to the further next MSM5299C's ER (EL) pin.
• CP
Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to the 4-bit parallel
shift register at the falling edge of the clock pulse.
• SHL
ER and EL can be used as either an input pin or an output pin based on the H/L condition of
SHL. The shift direction of each data (D0 to D3), the Input/Output condition of ER and EL
and the H/L condition of SHL are described in the table below.
SHL
L
H
ER
Input
EL
Output
Output
Input
Shift direction
D0
O1
O5
O77
D1
O2
O6
O78
D2
O3
O7
O79
D3
O4
O8
O80
D0
O80
O76
O4
D1
O79
O75
O3
D2
O78
O74
O2
D3
O77
O73
O1
end data
start data
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