RM7065A™ Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
List of Figures
Figure 1 Block Diagram .............................................................................................................10
Figure 2 CP0 Registers .............................................................................................................12
Figure 3 Instruction Issue Paradigm ..........................................................................................13
Figure 4 Pipeline ........................................................................................................................14
Figure 5 CP0 Registers .............................................................................................................19
Figure 6 Kernel Mode Virtual Addressing (32-bit) .....................................................................20
Figure 7 Typical Embedded System Block Diagram .................................................................27
Figure 8 Processor Block Read .................................................................................................29
Figure 9 Processor Block Write .................................................................................................30
Figure 10 Multiple Outstanding Reads ......................................................................................30
Figure 11 Clock Timing ..............................................................................................................47
Figure 12 Input Timing ...............................................................................................................47
Figure 13 Output Timing ............................................................................................................47
Figure 14 Mechanical Diagram .................................................................................................48
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Document ID: PMC-2010145, Issue 2